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45 条记录 (耗时 0.019 秒)

    Device and Method for Merging Different Video Codec
    21.
    发明申请
    Device and Method for Merging Different Video Codec 失效
    用于合并不同视频编解码器的设备和方法

    公开(公告)号：US20080037649A1

    公开(公告)日：2008-02-14

    申请号：US11665848

    申请日：2005-10-21

    申请人： Euee-S. Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sun-Won Park ,  Jong-Woo Won ,  Yong-Ho Cho ,  Chung-Ku Lee

    发明人： Euee-S. Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sun-Won Park ,  Jong-Woo Won ,  Yong-Ho Cho ,  Chung-Ku Lee

    IPC分类号： H04N7/24 ,  H04N7/12

    CPC分类号： H04N19/12 ,  H04N19/44 ,  H04N19/61 ,  H04N19/70

    摘要： The present invention is directed to a video unified codec device and its method. According to an embodiment of this invention, the unified codec device comprises parsing and decoding functional units (PD FUs) extracting and grouping context information, control signals, and data in bit streams inputted according to different syntax data per codec, macro-block-based functional units (MB-based FUs) unified based on block-based process units of each codec, for decoding data outputted from PD FUs, and a global control unit (GCU) for controlling MB-based FUs grouped after corresponding control signals and context information received from PD FUs to each codec and processing. By this invention, a new concept and structure of unified codec corresponding to similarities, differences, and considerations between different codecs can be presented.

    摘要翻译： 本发明涉及一种视频统一编解码器装置及其方法。 根据本发明的实施例，统一编解码器装置包括解码和解码功能单元（PD FU），提取和分组根据每个编解码器的不同语法数据输入的比特流的上下文信息，控制信号和数据，基于宏块 基于每个编解码器的基于块的处理单元统一的功能单元（基于MB的FU），用于解码从PD FU输出的数据;以及全局控制单元（GCU），用于控制在对应的控制信号和上下文信息之后分组的基于MB的FU 从PD FUs接收到每个编解码器和处理。 通过本发明，可以呈现对应于不同编解码器之间的相似性，差异和考虑的统一编解码器的新概念和结构。

    METHOD OF PREPARING BATTERY CORE PACK
    22.
    发明申请
    METHOD OF PREPARING BATTERY CORE PACK 有权
    电池芯片的制备方法

    公开(公告)号：US20070126394A1

    公开(公告)日：2007-06-07

    申请号：US11561033

    申请日：2006-11-17

    申请人： Hyeongchan KIM ,  Sain PARK ,  Yong-ho CHO

    发明人： Hyeongchan KIM ,  Sain PARK ,  Yong-ho CHO

    IPC分类号： H02J7/00

    CPC分类号： H01M10/4207 ,  H01M2/022 ,  H01M2/204

    摘要： Disclosed herein is a method of manufacturing a battery core pack having a plurality of unit cells, especially a plurality of cylindrical batteries, which are connected with each other by connecting members. According to the present invention, the structure of the battery core pack can be easily modified by merely changing the combination of the connecting members without manufacturing additional connecting members. Consequently, common use of the connecting members is possible.

    摘要翻译： 本文公开了一种制造具有多个单元电池，特别是多个圆柱形电池的电池芯组件的方法，它们通过连接构件相互连接。 根据本发明，通过仅仅改变连接构件的组合而不制造附加的连接构件，可以容易地改变电池芯组的结构。 因此，可以通常使用连接构件。

    Low density parity code encoding device and decoding device and encoding and decoding methods thereof
    25.
    发明授权
    Low density parity code encoding device and decoding device and encoding and decoding methods thereof 有权
    低密度奇偶校验码编码装置及解码装置及其编解码方法

    公开(公告)号：US08281206B2

    公开(公告)日：2012-10-02

    申请号：US12268534

    申请日：2008-11-11

    申请人： Hyun Ho Choi ,  Kyung Hun Jang ,  Jung Hyun Park ,  Yong Ho Cho ,  Dong Jo Park

    发明人： Hyun Ho Choi ,  Kyung Hun Jang ,  Jung Hyun Park ,  Yong Ho Cho ,  Dong Jo Park

    IPC分类号： H03M13/00

    CPC分类号： H03M13/356 ,  H03M13/1102 ,  H03M13/1148 ,  H03M13/353 ,  H04L1/0009 ,  H04L1/04

    摘要： A low density parity code (LDPC) encoding and decoding devices and encoding and decoding methods thereof are provided. An LDPC encoding device includes an information obtaining unit which obtains status information of at least two frequency bands, a matrix generation unit which generates a parity check matrix based on the status information, the parity check matrix including sub matrices which correspond to the at least two frequency bands, and an encoder which generates data bits and parity bits using an LDPC with the generated parity check matrix.

    摘要翻译： 提供了一种低密度奇偶校验码（LDPC）编码和解码装置及其编码和解码方法。 LDPC编码装置包括获取至少两个频带的状态信息的信息获取单元，基于状态信息生成奇偶校验矩阵的矩阵生成单元，所述奇偶校验矩阵包括对应于所述至少两个频带的子矩阵 频带，以及使用具有所生成的奇偶校验矩阵的LDPC生成数据位和奇偶校验位的编码器。

    Device and method for merging different video codec
    26.
    发明授权
    Device and method for merging different video codec 失效
    用于合并不同视频编解码器的设备和方法

    公开(公告)号：US08149922B2

    公开(公告)日：2012-04-03

    申请号：US11665848

    申请日：2005-10-21

    申请人： Euee-S. Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sung-Won Park ,  Jong-Woo Won ,  Yong Ho Cho ,  Chung-Ku Lee

    发明人： Euee-S. Jang ,  Yung-Lyul Lee ,  Sun-Young Lee ,  Sung-Won Park ,  Jong-Woo Won ,  Yong Ho Cho ,  Chung-Ku Lee

    IPC分类号： H04N7/12

    CPC分类号： H04N19/12 ,  H04N19/44 ,  H04N19/61 ,  H04N19/70

    摘要： A video unified codec device and corresponding video method. The unified codec device includes parsing and decoding functional units (PD FUs) extracting and grouping context information, control signals, and data in bit streams inputted according to different syntax data per codec, macro-block-based functional units (MB-based FUs) comprising block-based process units of each codec, for decoding data outputted from PD FUs, and a global control unit (GCU) for controlling MB-based FUs grouped after corresponding control signals and context information received from PD FUs to each codec and processing.

    摘要翻译： 视频统一编解码器设备及相应的视频方式。 统一编解码器装置包括解码和解码功能单元（PD FU），提取和分组根据每个编解码器的不同语法数据输入的比特流的上下文信息，控制信号和数据，基于宏块的功能单元（基于MB的功能单元） 包括用于解码从PDFU输出的数据的每个编解码器的基于块的处理单元，以及用于控制在对应的控制信号之后分组的基于MB的FU以及从PDFU接收的上下文信息到每个编解码器和处理的全局控制单元（GCU）。

    Integral cap assembly having protective circuit module, and secondary battery comprising the same
    27.
    发明授权
    Integral cap assembly having protective circuit module, and secondary battery comprising the same 有权
    具有保护电路模块的整体式盖组件和包括该组件的二次电池

    公开(公告)号：US07985501B2

    公开(公告)日：2011-07-26

    申请号：US12630449

    申请日：2009-12-03

    申请人： Hyungchan Kim ,  Hee gyu Kim ,  Yong-ho Cho ,  Jae sik Chung

    发明人： Hyungchan Kim ,  Hee gyu Kim ,  Yong-ho Cho ,  Jae sik Chung

    IPC分类号： H01M2/00

    CPC分类号： H01M2/0404 ,  H01M2/34 ,  H01M10/0436 ,  H01M10/425 ,  H01M2200/10 ,  Y10T29/4911

    摘要： An integral cap assembly comprising a top cap mounted as a base plate to an opening of a battery can and a cap subassembly including a protective circuit module and the like integrally mounted on the top cap, a method for manufacturing a secondary battery comprising the same, and a secondary battery manufactured thereby are disclosed. The cap assembly is provided as an integral member comprising the top cap acting as the base plate, and the cap subassembly having the protective circuit module provided thereon, thereby simplifying a manufacturing process of the battery while minimizing frequency of defective products. Additionally, the integral cap assembly is manufactured through insert injection molding, thereby providing notable advantages over the conventional technology.

    摘要翻译： 一种整体盖组件，包括顶盖，其安装成电池罐的开口的基板，以及包括一体地安装在顶盖上的保护电路模块等的盖子组件，包括该顶盖的二次电池的制造方法， 并且公开了由此制造的二次电池。 帽组件设置为整体构件，其包括用作基板的顶盖，并且帽子组件具有设置在其上的保护电路模块，从而简化了电池的制造过程，同时使缺陷产品的频率最小化。 此外，通过插入式注射成型制造整体式盖组件，从而提供了超过常规技术的显着优点。

    SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY CIRCUIT
    28.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY CIRCUIT 有权
    包含可变延迟电路的半导体存储器件

    公开(公告)号：US20100246295A1

    公开(公告)日：2010-09-30

    申请号：US12731465

    申请日：2010-03-25

    申请人： Dong-Su JANG ,  Yong-Ho CHO

    发明人： Dong-Su JANG ,  Yong-Ho CHO

    IPC分类号： G11C7/00 ,  G11C7/06

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.

    摘要翻译： 一种半导体存储器件包括被配置为将数据输出到一对位线的存储单元，可变延迟电路，被配置为接收读出放大器使能信号，通过改变基于a的延迟的斜率来调整读出放大器使能信号的延迟 可变外部电源电压，并输出延迟读出放大器使能信号;以及位线读出放大器，被配置为响应延迟的读出放大器使能信号放大该对位线之间的电压差，并将放大的电压差输出到一对 输入/输出线。

    Method and apparatus for controlling read latency of high-speed DRAM
    30.
    发明授权
    Method and apparatus for controlling read latency of high-speed DRAM 有权
    控制高速DRAM读延迟的方法和装置

    公开(公告)号：US07751261B2

    公开(公告)日：2010-07-06

    申请号：US12010700

    申请日：2008-01-29

    申请人： Yong-ho Cho

    发明人： Yong-ho Cho

    IPC分类号： G11C7/00

    CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

    摘要： Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

    摘要翻译： 提供了一种用于控制高速DRAM的读延迟的方法和装置。 存储器件可以包括延迟测量单元，延迟锁定环路，等待时间计数器和数据输出缓冲器。 延迟测量单元测量输入外部时钟信号和输出读取数据之间的延迟时间，以产生测量信号，并产生从外部时钟信号延迟的第一内部时钟信号。 延迟锁定环（DLL）接收第一内部时钟信号并产生与外部时钟信号同步的第二内部时钟信号。 延迟计数器响应于测量信号从外部读取命令信号产生等待时间信号，并且数据输出缓冲器响应等待时间信号和第二内部时钟信号输出读取的数据。