公开(公告)号：US06753584B1

公开(公告)日：2004-06-22

申请号：US09476558

申请日：2000-01-03

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L310232

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/318 ,  H01L21/32139 ,  H01L27/1462 ,  H01L31/02161 ,  H01L31/02327 ,  Y10S430/151

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns. One preferred material for the inventive antireflective layer includes metal silicon nitride ternary compounds of the general formula MxSiyNz wherein M is at least one transition metal, x is less than y, and z is in a range from about 0 to about 5y. Preferably, the Si will exceed M by about a factor of two. Addition of N is controlled by the ratio in the sputtering gas such as Ar/N. Tungsten is a preferred transition metal in the fabrication of the inventive antireflective coating. A preferred tungsten silicide target will have a composition of silicon between 1 and 4 in stoichiometric ratio to tungsten. Composite antireflective layers made of metal silicide binary compounds or metal silicon nitride ternary compounds may be fashioned according to the present invention depending upon a specific application.

Abstract translation: 根据本发明的抗反射结构包括层叠的金属氮化硅组合物，该层被叠加在待图案化的层上，这将在光致抗蚀剂图案化期间另外引起破坏性的反射率。 抗反射结构具有吸收光致抗蚀剂图案化期间使用的光的能力。 抗反射结构还具有将未吸收的光散射到对暴露于图案和强度的光致抗蚀剂材料无效的图案和强度的能力。本发明的优选的抗反射结构包括其上具有至少一层含硅的 金属或含硅金属氮化物。 半导体衬底将优选地具有宽度尺寸小于约0.5微米，更优选小于约0.25微米的特征尺寸。用于本发明的抗反射层的一种优选材料包括通式为MxSiyNz的金属氮化硅三元化合物，其中M为 至少一种过渡金属x小于y，z在约0至约5y的范围内。 优选地，Si将超过M约2倍。 N的添加由溅射气体中的比例如Ar / N控制。 在本发明的抗反射涂层的制造中，钨是优选的过渡金属。 优选的硅化钨靶将具有与钨的化学计量比为1至4的硅组成。 由金属硅化物二元化合物或金属氮化硅三元化合物制成的复合抗反射层可根据具体应用根据本发明制成。

公开(公告)号：US06214711B1

公开(公告)日：2001-04-10

申请号：US09139583

申请日：1998-08-25

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L213205

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.

Abstract translation: 通过将合金或复合靶溅射到凹槽中，将合金或复合材料沉积在半导体衬底的凹陷特征中，以形成第一沉积材料层。 第一沉积材料层以低角度和低能量被重新投射，以将第一沉积材料层重新沉积到凹槽的底部上，作为具有不同于第一沉积材料的化学计量的第二沉积材料层。 在另一实施例中，溅射室环境由氩和氮组成。 在又一个实施例中，再溅射步骤之后是沉积具有与第二沉积层不同的化学计量比的至少一层材料，以形成沉积在凹槽中的材料的“分级”化学计量。

公开(公告)号：US5863393A

公开(公告)日：1999-01-26

申请号：US964575

申请日：1997-11-05

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: C23C14/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01L21/768

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.

Abstract translation: 通过将合金或复合靶溅射到凹槽中，将合金或复合材料沉积在半导体衬底的凹陷特征中，以形成第一沉积材料层。 第一沉积材料层以低角度和低能量被重新投射，以将第一沉积材料层重新沉积到凹槽的底部上，作为具有不同于第一沉积材料的化学计量的第二沉积材料层。 在另一实施例中，溅射室环境由氩和氮组成。 在又一个实施例中，再溅射步骤之后是沉积具有与第二沉积层不同的化学计量比的至少一层材料，以形成沉积在凹槽中的材料的“分级”化学计量。

公开(公告)号：US20060263963A1

公开(公告)日：2006-11-23

申请号：US11495654

申请日：2006-07-28

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

公开(公告)号：US20050250275A1

公开(公告)日：2005-11-10

申请号：US11180288

申请日：2005-07-13

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract translation: 描述了在半导体组件上形成互补晶体管的互补晶体管和方法。 晶体管可以由覆盖在用于PMOS和NMOS区域导电掺杂的半导体衬底上的电介质材料上的缺陷硅键合原子的金属硅化合物形成。 覆盖在NMOS区域上的金属硅化合物被转换为金属氮化硅，并且覆盖PMOS区域的金属硅化合物转化为金属硅化物。 可以形成包括金属氮化硅的NMOS晶体管栅电极和包括金属硅化物的PMOS晶体管栅电极。

公开(公告)号：US20050000942A1

公开(公告)日：2005-01-06

申请号：US10881503

申请日：2004-06-29

Applicant: Whonchee Lee ,  Yongjun Hu

Inventor： Whonchee Lee ,  Yongjun Hu

IPC: C23F1/28 ,  H01L21/3213 ,  H01L21/768 ,  C23F1/00

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide. An etching composition including a mineral acid and a peroxide, preferably, HCl and hydrogen peroxide, is also described. The etching methods and compositions may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.

Abstract translation: 用于集成电路制造的蚀刻方法包括在衬底组件上提供金属氮化物层，在金属氮化物层的第一部分上提供钴硅化物的区域，以及在金属氮化物层的第二部分上提供钴区域。 用至少一种包含无机酸和过氧化物的溶液除去钴的区域和金属氮化物层的第二部分。 无机酸可以选自HCl，H 2 SO 4，H 3 PO 4，HNO 3和稀HF（优选无机酸是HCl），并且过氧化物可以是过氧化氢。 此外，去除钴的区域和金属氮化物层的第二部分可以包括一步法或两步法。 在一步法中，用包含无机酸和过氧化物的单一溶液除去钴的区域和金属氮化物层的第二部分。 在两步法中，用含有无机酸和过氧化物的第一溶液除去钴的区域，并用含有过氧化物的第二溶液除去金属氮化物层的第二部分。 还描述了包含无机酸和过氧化物，优选HCl和过氧化氢的蚀刻组合物。 蚀刻方法和组合物可以用于形成诸如字线，栅电极，局部互连等的结构。

公开(公告)号：US06689685B2

公开(公告)日：2004-02-10

申请号：US10271259

申请日：2002-10-15

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2144

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal suicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种用于制造光滑并具有大的扩散阻挡材料的氮化物晶粒的膜的方法。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境氮含量，使得扩散阻挡材料的氮化物核均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长扩散阻挡材料的大的氮化物晶粒的膜。 还公开了一种适合于MOS存储器电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻微氮化难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US06680246B2

公开(公告)日：2004-01-20

申请号：US10271126

申请日：2002-10-15

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L214763

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal silicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种用于制造光滑并具有大的扩散阻挡材料的氮化物晶粒的膜的方法。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境氮含量，使得扩散阻挡材料的氮化物核均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长扩散阻挡材料的大的氮化物晶粒的膜。 还公开了一种适合于MOS存储器电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻度氮化难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US06445045B1

公开(公告)日：2002-09-03

申请号：US09906464

申请日：2001-07-16

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2976

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.2 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

公开(公告)号：US06436818B1

公开(公告)日：2002-08-20

申请号：US09455115

申请日：1999-12-06

Applicant: Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P. S. Thakur ,  Scott DeBoer

Inventor： Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P. S. Thakur ,  Scott DeBoer

IPC: H01L2976

CPC classification number: H01L21/28044 ,  H01L21/28052 ,  H01L29/4941

Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

Abstract translation: 用于形成字线堆叠的方法和装置包括以下的一个或组合：掺杂有氧或氮的硅扩散阻挡层，耦合在底部硅层和导体层之间; 耦合在多晶硅层和导体层之间的非晶硅扩散势垒; 耦合在底部硅层和硅化钛导体层之间的薄氮化物层和耦合到导体层的底部硅层，其包含C54-硅酸钛。 通过本发明的方法形成的字线叠层用于0.25μm以下的线宽应用，并具有较低的电阻率和改善的热稳定性。