公开(公告)号：US10592279B2

公开(公告)日：2020-03-17

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/34 ,  G06F9/50

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20190252385A1

公开(公告)日：2019-08-15

申请号：US15895799

申请日：2018-02-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  David A. Roberts

IPC: H01L27/108 ,  G11C11/406 ,  G11C11/408

CPC classification number: H01L27/10805 ,  G11C11/40611 ,  G11C11/4085

Abstract: A modified 1C1T cell detects when the charge in the memory cell drops below a predetermined voltage due to leakage and asserts a refresh signal indicating that refresh needs to be performed on those memory cells associated with the modified 1C1T memory cell. The associated memory cells may be a row, a bank, or other groupings of memory cells. Because temperature affects leakage current, the modified memory cell automatically adjusts for temperature.

公开(公告)号：US20190196742A1

公开(公告)日：2019-06-27

申请号：US15851476

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Jiasheng Chen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F9/3887 ,  G06T1/20 ,  G06T1/60

Abstract: A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

公开(公告)号：US20190065100A1

公开(公告)日：2019-02-28

申请号：US15686121

申请日：2017-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov

IPC: G06F3/06 ,  G06F12/0868

Abstract: A method and apparatus of performing a memory operation includes receiving a memory operation request at a first memory controller that is in communication with a second memory controller. The first memory controller forwards the memory operation request to the second memory controller. Upon receipt of the memory operation request, the second memory controller provides first information or second information depending on a condition of a pseudo-bank of the second memory controller and a type of the memory operation request.

公开(公告)号：US20170371720A1

公开(公告)日：2017-12-28

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20170168546A1

公开(公告)日：2017-06-15

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20170147228A1

公开(公告)日：2017-05-25

申请号：US14952517

申请日：2015-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  David A. Roberts ,  Mitesh R. Meswani ,  Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F3/06

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/4022 ,  G06F15/7821 ,  G06F2212/1024

Abstract: A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

公开(公告)号：US20160085551A1

公开(公告)日：2016-03-24

申请号：US14490213

申请日：2014-09-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph L. Greathouse ,  Mitesh R. Meswani ,  Sooraj Puthoor ,  Dmitri Yudanov ,  James M. O'Connor

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3887 ,  G06F9/3851

Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

Abstract translation: 呈现并行执行多个线程的计算单元。 计算单元包括一个或多个单指令多数据（SIMD）单元和读取和解码逻辑。 SIMD单元具有不同数量的算术逻辑单元（ALU），使得每个SIMD单元可以执行不同数量的线程。 获取和解码逻辑与每个SIMD单元通信，并且被配置为基于这样不同数量的ALU将线程分配给SIMD单元以供执行。