公开(公告)号：US11341069B2

公开(公告)日：2022-05-24

申请号：US17068660

申请日：2020-10-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Bryan P Broussard ,  Paul Moyer ,  Eric Christopher Morton ,  Pravesh Gupta

IPC: G06F13/26 ,  G06F12/0875 ,  G06F13/40

Abstract: A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.

公开(公告)号：US11321245B2

公开(公告)日：2022-05-03

申请号：US16681617

申请日：2019-11-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer

IPC: G06F12/00 ,  G06F12/123 ,  G06F12/0862

Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.

公开(公告)号：US11106600B2

公开(公告)日：2021-08-31

申请号：US16256634

申请日：2019-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Paul Moyer

IPC: G06F12/10 ,  G06F12/126 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/1027

Abstract: A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.

公开(公告)号：US10366027B2

公开(公告)日：2019-07-30

申请号：US15826065

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Eric Christopher Morton ,  Elizabeth Cooper ,  William L. Walker ,  Douglas Benson Hunt ,  Richard Martin Born ,  Richard H. Lee ,  Paul C. Miranda ,  Philip Ng ,  Paul Moyer

IPC: G06F13/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.