公开(公告)号：US20180286942A1

公开(公告)日：2018-10-04

申请号：US15474043

申请日：2017-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768

Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

公开(公告)号：US20240304241A1

公开(公告)日：2024-09-12

申请号：US18181054

申请日：2023-03-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  Kerrie Vercant Underhill

IPC: G11C11/419 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

CPC classification number: G11C11/419 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696 ,  H10B10/125

Abstract: An apparatus and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses pairs of transistors that are vertically stacked gate all around (GAA) transistors with gate terminals forming a T-shape with respect to one another and a single gate contact that overlaps only one active layer of the two active layers of the pair. Transistors of such a pair of field effect transistors (FETs) are referred to as TFETs. With respect to one another, the active layers of TFETs use opposite doping polarities and conduct current in an orthogonal direction. A non-overlapping distance between top and bottom active layers of a pair of TFETs is at least a width of a drain/source contact. The orthogonal current flow of the top and bottom active layers simplifies local connections that reduces the resistance and capacitance of the signal routes.

公开(公告)号：US20240258322A1

公开(公告)日：2024-08-01

申请号：US18401038

申请日：2023-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

公开(公告)号：US20240128192A1

公开(公告)日：2024-04-18

申请号：US18047482

申请日：2022-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Suphachai Sutanthavibul ,  Richard T. Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes a micro through silicon via (TSV) that traverses a silicon substrate layer to a backside metal layer. The integrated circuit also includes power switches. The integrated circuit routes a power supply signal from the output of a power switch to a frontside power rail using the micro TSV and the backside metal layer. The integrated circuit also routes the power supply signal from the output of the power switch to the frontside power rail using a frontside metal layer. Therefore, the frontside metal layer and the backside metal layer provide power connection redundancy that increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. In addition, the process routes a ground reference voltage level using both a frontside power rail and a backside power rail.

公开(公告)号：US20240032270A1

公开(公告)日：2024-01-25

申请号：US18480463

申请日：2023-10-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H10B10/00 ,  G11C7/10 ,  H01L29/423

CPC classification number: H10B10/12 ,  G11C7/1045 ,  H01L29/42392

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.

公开(公告)号：US11778803B2

公开(公告)日：2023-10-03

申请号：US17489252

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G11C7/10 ,  H10B10/00 ,  H01L29/423

CPC classification number: H10B10/12 ,  G11C7/1045 ,  H01L29/42392

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.

公开(公告)号：US20230102901A1

公开(公告)日：2023-03-30

申请号：US17489221

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A system and method for creating layout for standard cells are described. In various implementations, a standard cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The direction of current flow of the top GAA transistor is orthogonal to the direction of current flow of the bottom GAA transistor. The channels of the vertically stacked transistors use opposite doping polarities. The orthogonal orientation allows both the top and bottom GAA transistors to have the maximum mobility for their respective carriers based on their orientation. The Cross FETs utilize a single metal layer and a single via layer for connections between the top and bottom GAA transistors.

公开(公告)号：US20230092184A1

公开(公告)日：2023-03-23

申请号：US17483672

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

公开(公告)号：US11347925B2

公开(公告)日：2022-05-31

申请号：US15636278

申请日：2017-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G06F30/394 ,  G06F30/39 ,  G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

公开(公告)号：US20220093504A1

公开(公告)日：2022-03-24

申请号：US17030830

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  John J. Wuu

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522 ,  G11C11/418 ,  G11C11/419 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.