公开(公告)号：US11782845B2

公开(公告)日：2023-10-10

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Joseph Michael Pusdesris ,  Abhishek Raja ,  Karthik Sundaram ,  Anoop Ramachandra Iyer ,  Michael Brian Schinzler ,  James David Dundas ,  Yasuo Ishii

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US11775440B2

公开(公告)日：2023-10-03

申请号：US17579842

申请日：2022-01-20

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Balaji Vijayan ,  Karthik Sundaram ,  Yasuo Ishii ,  Joseph Michael Pusdesris

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602

Abstract: Indirect prefetch circuitry initiates a producer prefetch requesting return of producer data having a producer address and at least one consumer prefetch to request prefetching of consumer data having a consumer address derived from the producer data. A producer prefetch filter table stores producer filter entries indicative of previous producer addresses of previous producer prefetches. Initiation of a requested producer prefetch for producer data having a requested producer address is suppressed when a lookup of the producer prefetch filter table determines that the requested producer address hits against a producer filter entry of the table. The lookup of the producer prefetch filter table for the requested producer address depends on a subset of bits of the requested producer address including at least one bit which distinguishes different chunks of data within a same cache line.

公开(公告)号：US10901742B2

公开(公告)日：2021-01-26

申请号：US16364570

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken. During each prediction iteration, the prediction circuitry is arranged by default to access a prediction storage in order to produce prediction information for instructions associated with a specified block of instruction addresses (including at least the predict block being considered), and to use that prediction information to make the prediction for the predict block. Buffer storage is used to retain the prediction information obtained from the prediction storage during one or more previous prediction iterations, and detection circuitry is used to detect when a current predict block being considered during a current prediction iteration comprises one or more instruction addresses for which the associated prediction information is retained in the buffer storage. In that event, the above default behaviour is not adopted, and an override condition is triggered to cause the prediction information for those one or more instruction addresses to be obtained from the buffer storage rather than from the prediction storage, giving rise to a power saving.

公开(公告)号：US10819736B2

公开(公告)日：2020-10-27

申请号：US15825524

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt ,  Yasuo Ishii

IPC: H04L29/06 ,  G06F9/38 ,  G06F21/53 ,  G06F21/78

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

公开(公告)号：US12175251B2

公开(公告)日：2024-12-24

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew Harris ,  Alexander Cole Shulyak ,  . Abhishek Raja ,  Bipin Prasad Heremagalur Ramaprasad ,  William Elton Burky ,  Li Ma ,  Michael David Achenbach ,  Nicholas Andrew Plante ,  Yasuo Ishii

IPC: G06F9/38

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US11983533B2

公开(公告)日：2024-05-14

申请号：US17851266

申请日：2022-06-28

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Alexander Cole Shulyak ,  Yasuo Ishii ,  Houdhaifa Bouzguarrou

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3861

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

公开(公告)号：US11861368B2

公开(公告)日：2024-01-02

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Michael Brian Schinzler ,  Yasuo Ishii ,  Jatin Bhartia ,  Sumanth Chengad Raghu

IPC: G06F9/38 ,  G06F21/50 ,  G06F9/48

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F9/48 ,  G06F21/50

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US11526359B2

公开(公告)日：2022-12-13

申请号：US16150372

申请日：2018-10-03

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

公开(公告)号：US11507372B2

公开(公告)日：2022-11-22

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Yasuo Ishii ,  Muhammad Umar Farooq ,  Jason Lee Setter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US11455253B2

公开(公告)日：2022-09-27

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  James David Dundas ,  Chang Joo Lee ,  Muhammad Umar Farooq

IPC: G06F12/0864 ,  G06F12/121 ,  G06F12/0873 ,  G06F12/0811

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.