公开(公告)号：US12174738B2

公开(公告)日：2024-12-24

申请号：US17885780

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, Jr.

IPC: G06F12/0802

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

公开(公告)号：US20240004796A1

公开(公告)日：2024-01-04

申请号：US18331324

申请日：2023-06-08

Applicant: Arm Limited

Inventor： Andrew David Tune

IPC: G06F12/0831 ,  G06F12/0871

CPC classification number: G06F12/0831 ,  G06F12/0871

Abstract: An apparatus comprises an non-inclusive cache (14) configured to cache data and coherency control circuitry (16). The coherency control circuitry is configured to look up the non-inclusive cache in response to a coherent access request from a first requestor (4). In response to determining that the coherent access request can be serviced using data stored in a matching entry of the non-inclusive cache, the coherency control circuitry references snoop-filter information associated with the matching entry to determine whether the first requestor can use the data stored in the matching entry without waiting for a response to a snoop of a coherent cache (8).

公开(公告)号：US11288195B2

公开(公告)日：2022-03-29

申请号：US16361548

申请日：2019-03-22

Applicant: Arm Limited

Inventor： Andrew David Tune

IPC: G06F12/0817 ,  G06F12/0882 ,  G06F12/1027 ,  G06F9/54

Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to the issue of the one or more data handling instructions to the one or more given nodes.

公开(公告)号：US10938622B2

公开(公告)日：2021-03-02

申请号：US16423386

申请日：2019-05-28

Applicant: Arm Limited

Inventor： Julian Jose Hilgemberg Pontes ,  Andrew David Tune ,  Sean James Salisbury

IPC: H04L12/24 ,  H04L12/46

Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location. The fault detection circuitry is arranged to receive upstream digests from the upstream location and corresponding downstream digests received via a return path from each downstream location, and to determine presence of the fault condition based on a comparison of each upstream digest with its corresponding downstream digest.

公开(公告)号：US10289587B2

公开(公告)日：2019-05-14

申请号：US15139559

申请日：2016-04-27

Applicant: ARM Limited

Inventor： Ian David Andrews ,  Andrew David Tune ,  Daniel Adam Sara ,  George Robert Scott Lloyd

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/36

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

公开(公告)号：US09906440B2

公开(公告)日：2018-02-27

申请号：US14734367

申请日：2015-06-09

Applicant: ARM LIMITED

Inventor： Rakesh Raman ,  Andrew David Tune ,  Guanghui Geng

IPC: H04L12/937 ,  H04L12/753 ,  G06F13/14

CPC classification number: H04L45/48 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.

公开(公告)号：US09442878B2

公开(公告)日：2016-09-13

申请号：US14255352

申请日：2014-04-17

Applicant: ARM LIMITED

Inventor： Daniel Sara ,  Andrew David Tune

IPC: G06F12/00 ,  G06F13/42

CPC classification number: G06F13/4221

Abstract: A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction.

Abstract translation: 系统级芯片集成电路包括用于将事务源与事务目的地连接的互连电路。 缓冲电路缓冲从交易源接收到的多个访问事务，然后它们被传递到相应的事务目的地。 诸如标识符重用电路之类的危险检查电路与窥探电路执行的窥探操作并行执行危险检查，用于管理存储在多个高速缓冲存储器中的数据值之间的相干性。 窥探电路包括窥探重排序电路，用于允许窥探响应的重新排序。 侦听电路可以对与该事务执行一个或多个危险检查的危险检查电路并行地发出对于给定访问事务的窥探请求。

公开(公告)号：US09176856B2

公开(公告)日：2015-11-03

申请号：US13936749

申请日：2013-07-08

Applicant: ARM Limited

Inventor： Andrew David Tune

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0223 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0895 ,  Y02D10/13

Abstract: A data store has a data array for storing data values and a tag array for storing tag values for tracking which data values are stored in the data array. The associativity of the data array is greater than the associativity of the tag array. This means that fewer tag entries need to be accessed on each data access than in a conventional data store, reducing power consumption.

Abstract translation: 数据存储具有用于存储数据值的数据阵列和用于存储用于跟踪哪些数据值被存储在数据阵列中的标签值的标签阵列。 数据阵列的关联性大于标签数组的关联性。 这意味着在传统数据存储中，每个数据访问需要访问较少的标签条目，从而降低功耗。

公开(公告)号：US20250068563A1

公开(公告)日：2025-02-27

申请号：US18947239

申请日：2024-11-14

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

IPC: G06F12/0802

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

公开(公告)号：US11314676B2

公开(公告)日：2022-04-26

申请号：US14944340

申请日：2015-11-18

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16 ,  G06F13/42

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.