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    Dynamic Power Management for On-Chip Memory
    1.
    发明公开
    Dynamic Power Management for On-Chip Memory 审中-公开

    公开(公告)号：US20240055035A1

    公开(公告)日：2024-02-15

    申请号：US17885753

    申请日：2022-08-11

    Applicant: Arm Limited

    Inventor： Edward Martin McCombs, JR.

    IPC: G11C8/08 ,  G11C8/10

    CPC classification number: G11C8/08 ,  G11C8/10

    Abstract: Dynamic power management for an on-chip memory, such as a system cache memory as well as other memories, is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section.

    Circuitry and Method
    2.
    发明申请
    Circuitry and Method 有权

    公开(公告)号：US20250068563A1

    公开(公告)日：2025-02-27

    申请号：US18947239

    申请日：2024-11-14

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

    IPC: G06F12/0802

    Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

    System Cache Peak Power Management
    7.
    发明公开
    System Cache Peak Power Management 审中-公开

    公开(公告)号：US20230154526A1

    公开(公告)日：2023-05-18

    申请号：US17530095

    申请日：2021-11-18

    Applicant: Arm Limited

    Inventor： Edward Martin McCombs, JR. ,  Hsin-Yu Chen

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076

    Abstract: Various implementations described herein are related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

    Dynamic Way-Based Variable Pipeline Architecture for On-Chip Memory
    9.
    发明公开
    Dynamic Way-Based Variable Pipeline Architecture for On-Chip Memory 审中-公开

    公开(公告)号：US20240055034A1

    公开(公告)日：2024-02-15

    申请号：US17885747

    申请日：2022-08-11

    Applicant: Arm Limited

    Inventor： Edward Martin McCombs, JR.

    IPC: G11C8/08 ,  G11C7/10 ,  G11C8/18

    CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/18

    Abstract: An on-chip memory is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section, and access the address.

    Circuitry and Method
    10.
    发明公开
    Circuitry and Method 审中-公开

    公开(公告)号：US20240054073A1

    公开(公告)日：2024-02-15

    申请号：US17885780

    申请日：2022-08-11

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

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