公开(公告)号：US20230133144A1

公开(公告)日：2023-05-04

申请号：US17518661

申请日：2021-11-04

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES ,  Jonatan Christoffer LÖVGREN

IPC: H03H17/02 ,  G06F9/38

Abstract: There is provided a data processing apparatus and method. The data processing apparatus comprises a filter circuit comprising storage circuitry to store program counter values and to assert a trigger signal in response to a lookup operation using a current program counter value hitting in the storage circuitry. The processing apparatus comprises a processing unit to generate an output in response to the trigger signal. The processing apparatus is provided with resolution circuitry, associated with a downstream processing stage, to determine whether the output is of use, and in that event to assert a false miss indication in the absence of the processing unit having been triggered to produce the output. The filter circuit is configured to maintain a trigger sensitivity metric in dependence on the false miss indication, and the chosen number of bits employed when performing the lookup operation is dependent on the trigger sensitivity metric.

公开(公告)号：US20210232400A1

公开(公告)日：2021-07-29

申请号：US16775431

申请日：2020-01-29

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES

IPC: G06F9/38 ,  G06F1/03

Abstract: A branch predictor provides a predicted branch instruction outcome for a current block of at least one instruction. The branch predictor comprises branch prediction tables to store branch prediction entries providing branch prediction information; lookup circuitry to perform, based on indexing information associated with the current block, a table lookup in a looked up subset of the branch prediction tables; and prediction generating circuitry to generate the predicted branch instruction outcome for the current block based on the branch prediction information in the branch prediction entries looked up in the looked up subset of branch prediction tables. The looked up subset of branch prediction tables is selected based on lookup filtering information obtained for the current block. Lookups to tables other than the looked up subset are suppressed.

公开(公告)号：US20210064528A1

公开(公告)日：2021-03-04

申请号：US16550607

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Matthew Andrew RAFACZ ,  Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/1027

Abstract: A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.

公开(公告)号：US20200082280A1

公开(公告)日：2020-03-12

申请号：US16541531

申请日：2019-08-15

Applicant: Arm Limited

Inventor： Luc ORION ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06N5/04 ,  G06N5/00 ,  G06N20/00 ,  G06F12/0862

Abstract: An apparatus comprises: a prediction storage structure comprising a plurality of prediction state entries representing instances of predicted instruction behaviour; prediction training circuitry to perform a training operation to train the prediction state entries based on actual instruction behaviour; prediction circuitry to output at least one control signal for triggering a speculative operation based on the predicted instruction behaviour represented by a prediction state entry for which the training operation has provided sufficient confidence in the predicted instruction behaviour; an allocation filter comprising at least one allocation filter entry representing a failed predicted instruction behaviour for which the training operation failed to provide said sufficient confidence; and prediction allocation circuitry to prevent allocation of a new entry in the prediction storage structure for a failed predicted instruction behaviour represented by an allocation filter entry of the allocation filter.

公开(公告)号：US20190303161A1

公开(公告)日：2019-10-03

申请号：US15939827

申请日：2018-03-29

Applicant: Arm Limited

Inventor： Luca NASSI ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES

IPC: G06F9/38 ,  G06F9/35

Abstract: An apparatus and method are provided for controlling branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry that comprises a plurality of branch prediction mechanisms used to predict target addresses for branch instructions to be executed by the processing circuitry. The branch instructions comprise a plurality of branch types, where one branch type is a return instruction. The branch prediction mechanisms include a return prediction mechanism used by default to predict a target address when a return instruction is detected by the branch prediction circuitry. However, the branch prediction circuitry is responsive to a trigger condition indicative of misprediction of the target address when using the return prediction mechanism to predict the target address for a given return instruction, to switch to using an alternative branch prediction mechanism for predicting the target address for the given return instruction. This has been found to improve performance in certain situations.

公开(公告)号：US20250068565A1

公开(公告)日：2025-02-27

申请号：US18455025

申请日：2023-08-24

Applicant: ARM Limited

Inventor： Houdhaifa BOUZGUARROU ,  Rami Mohammad AL SHEIKH ,  Guillaume BOLBENES

IPC: G06F12/0862

Abstract: Prediction circuitry generates a prediction associated with a prediction input address, for controlling a speculative action by a processor. The prediction circuitry comprises combiner circuitry to determine a combined prediction by applying a prediction combination function to a given address and sets of prediction information generated by a plurality of predictors corresponding to the given address. A combiner cache structure comprises combiner cache entries. A given combiner cache entry associated with an address indication indicates items of combined prediction information determined by the combiner circuitry for an address corresponding to the address indication and different combinations of possible values for the respective sets of prediction information. Combiner cache lookup circuitry looks up the combiner cache structure based on the prediction input address to identify a selected combiner cache entry, and generates the prediction based on a selected item of combined prediction information selected from the selected combiner cache entry based on the respective sets of prediction information generated by the predictors corresponding to the prediction input address.

公开(公告)号：US20230418611A1

公开(公告)日：2023-12-28

申请号：US17847378

申请日：2022-06-23

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30065 ,  G06F9/3844 ,  G06F9/3802

Abstract: Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data/instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N≥1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).

公开(公告)号：US20230409325A1

公开(公告)日：2023-12-21

申请号：US17838713

申请日：2022-06-13

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU ,  Luca NASSI

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/30145 ,  G06F9/30189 ,  G06F9/325 ,  G06F9/3867

Abstract: Processing circuitry performs processing operations in response to micro-operations. Front end circuitry supplies the micro-operations to be processed by the processing circuitry. Prediction circuitry generates a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry. The front end circuitry varies, based on a level of confidence in the prediction of the number of loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry.

公开(公告)号：US20230195467A1

公开(公告)日：2023-06-22

申请号：US17556166

申请日：2021-12-20

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3816 ,  G06F9/30054

Abstract: A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

公开(公告)号：US20210089472A1

公开(公告)日：2021-03-25

申请号：US16577271

申请日：2019-09-20

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU

IPC: G06F12/121 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises a cache comprising cache entries, each cache entry storing cached information and an entry usefulness value indicative of usefulness of the cached information. Base usefulness storage circuitry stores a base usefulness value. Cache replacement control circuitry controls, based on a usefulness level determined for a given cache entry, whether the given cache entry is selected for replacement. The cache replacement control circuitry determines the usefulness level for the given cache entry based on a difference between the entry usefulness value specified by the given cache entry and the base usefulness value stored in the base usefulness storage circuitry.