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公开(公告)号：US10140476B2
公开(公告)日：2018-11-27
申请号：US15189284
申请日：2016-06-22
Applicant: ARM LIMITED
Inventor： John Michael Horley , Michael John Williams , Simon John Craske , Uma Maheswari Ramalingam
IPC: G06F21/74
Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.
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公开(公告)号：US10120813B2
公开(公告)日：2018-11-06
申请号：US15452989
申请日：2017-03-08
Applicant: ARM Limited
Inventor： John Michael Horley , Dan Brook
IPC: G06F12/1009 , G06F12/1036
Abstract: Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.
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公开(公告)号：US09639361B2
公开(公告)日：2017-05-02
申请号：US14205438
申请日：2014-03-12
Applicant: ARM Limited
Inventor： Paul Anthony Gilkerson , John Michael Horley
CPC classification number: G06F9/30145 , G06F11/3471 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F2201/865 , G06F2201/88
Abstract: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behavior of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry.
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公开(公告)号：US11275670B2
公开(公告)日：2022-03-15
申请号：US16970771
申请日：2019-03-05
Applicant: Arm Limited
Inventor： John Michael Horley
Abstract: An apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, where the sequence of instructions comprises branch instructions. Trace generating circuitry generates a trace stream of trace items indicative of the data processing operations. The trace generating circuitry is responsive to one or more not-taken branch instructions followed by a taken branch instruction in the sequence of instructions to: include at least one not-taken trace item corresponding to the one or more not-taken branch instructions followed by a taken trace item in the trace stream when a current status condition of the apparatus is met, and to include a source address associated with the taken branch instruction in the trace stream when the current status condition of the apparatus is not met. A hybrid approach between tracing not-taken branch instructions and tracing a source address associated with the taken branch instruction is thus provided.
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Patent Agency Ranking
公开(公告)号：US10606679B2
公开(公告)日：2020-03-31
申请号：US15830380
申请日：2017-12-04
Applicant: Arm Limited
Inventor： Anitha Kona , Michael John Williams , John Michael Horley , Alasdair Grant
Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.
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公开(公告)号：US10439903B2
公开(公告)日：2019-10-08
申请号：US15191950
申请日：2016-06-24
Applicant: ARM LIMITED
Inventor： John Michael Horley , Christopher Vincent Severino
IPC: H04L12/26
Abstract: A system, apparatus and method for gathering monitoring data relating to the operation of a data processing system are disclosed. The data processing system comprises a monitor controller and a plurality of monitors which gather monitoring data relating to the operation of the data processing system. Each monitor does not send its monitoring data to the monitor controller unsolicited, but merely indicates to the monitor controller that it has such data ready for transmission. In response to reception of a data ready signal from more than one monitor, the monitor controller selects one of these monitors and sends it a data transmission command, thereby avoiding resource contention in a shared resource between data transmissions from more than one monitor.
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公开(公告)号：US10228942B2
公开(公告)日：2019-03-12
申请号：US15532286
申请日：2015-11-23
Applicant: ARM LIMITED
Inventor： Michael John Williams , John Michael Horley , Stephan Diestelhorst
Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.
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公开(公告)号：US09678852B2
公开(公告)日：2017-06-13
申请号：US14633630
申请日：2015-02-27
Applicant: ARM Limited
Inventor： John Michael Horley
CPC classification number: G06F11/3476 , G06F11/3065 , G06F11/3466 , G06F11/348 , G06F2201/88
Abstract: An apparatus for processing data is disclosed in which the operations of data processing circuitry are monitored by one or more trace data sources which generate items of trace data indicative of the data processing operations performed by the data processing circuitry. Trace data source identifiers in a resulting trace stream indicate the source of items of trace data and a selected trace data source identifier is included in the trace stream in response to a received flush request signal. All items of trace data generated before the apparatus received the flush request signal are included in the trace stream before the selected trace data source identifier, such that the conclusion of the response of the apparatus to the flush request signal can be identified.
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公开(公告)号：US09606850B2
公开(公告)日：2017-03-28
申请号：US13795611
申请日：2013-03-12
Applicant: ARM LIMITED
Inventor： John Michael Horley , Simon John Craske
CPC classification number: G06F11/0766 , G06F11/0721
Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.
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