公开(公告)号：US11004503B1

公开(公告)日：2021-05-11

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

公开(公告)号：US10748583B2

公开(公告)日：2020-08-18

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/22

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US10734065B2

公开(公告)日：2020-08-04

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

公开(公告)号：US20200219559A1

公开(公告)日：2020-07-09

申请号：US16820487

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US10600477B2

公开(公告)日：2020-03-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US12230317B2

公开(公告)日：2025-02-18

申请号：US18369794

申请日：2023-09-18

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Vidit Babbar

IPC: G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

公开(公告)号：US12159664B2

公开(公告)日：2024-12-03

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US11222670B2

公开(公告)日：2022-01-11

申请号：US16709687

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Cyrille Nicolas Dray ,  Ashish Bhardwaj ,  Durgesh Kumar Dubey

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

公开(公告)号：US20210335397A1

公开(公告)日：2021-10-28

申请号：US16860764

申请日：2020-04-28

Applicant: Arm Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi

IPC: G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

公开(公告)号：US10755774B2

公开(公告)日：2020-08-25

申请号：US16820487

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.