公开(公告)号：US20190325948A1

公开(公告)日：2019-10-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US09824749B1

公开(公告)日：2017-11-21

申请号：US15256200

申请日：2016-09-02

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Abhishek B. Akkur

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/409 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/12

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

公开(公告)号：US20230016339A1

公开(公告)日：2023-01-19

申请号：US17375887

申请日：2021-07-14

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Bikas Maiti ,  Vivek Nautiyal

IPC: G11C29/00 ,  G11C29/18 ,  G11C7/10

Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

公开(公告)号：US10147482B2

公开(公告)日：2018-12-04

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US20180268894A1

公开(公告)日：2018-09-20

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US11043262B2

公开(公告)日：2021-06-22

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US10748583B2

公开(公告)日：2020-08-18

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/22

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US20200219559A1

公开(公告)日：2020-07-09

申请号：US16820487

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US10600477B2

公开(公告)日：2020-03-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.