公开(公告)号：US11043262B2

公开(公告)日：2021-06-22

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US10748583B2

公开(公告)日：2020-08-18

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/22

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US10734065B2

公开(公告)日：2020-08-04

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

公开(公告)号：US20190237111A1

公开(公告)日：2019-08-01

申请号：US15881704

申请日：2018-01-26

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Satinderjit Singh ,  Abhishek B. Akkur ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Jungtae Kwon ,  Jitendra Dasani ,  Manoj Puthan Purayil

IPC: G11C5/06 ,  G11C7/06

CPC classification number: G11C5/063 ,  G11C7/06

Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

公开(公告)号：US11232833B2

公开(公告)日：2022-01-25

申请号：US15679325

申请日：2017-08-17

Applicant: ARM Limited

Inventor： Abhishek B. Akkur ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Satinderjit Singh ,  Vasimraja Bhavikatti

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C7/22 ,  G06F30/35 ,  G06F30/392 ,  G06F30/394 ,  G11C7/12 ,  G11C7/08 ,  G06F119/12

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

公开(公告)号：US20200005836A1

公开(公告)日：2020-01-02

申请号：US16024449

申请日：2018-06-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

公开(公告)号：US20190325949A1

公开(公告)日：2019-10-24

申请号：US15960482

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

公开(公告)号：US10425076B2

公开(公告)日：2019-09-24

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10269416B1

公开(公告)日：2019-04-23

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/417 ,  G11C11/418 ,  H01L23/528 ,  H01L27/11 ,  G11C11/412

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US10217496B1

公开(公告)日：2019-02-26

申请号：US15907951

申请日：2018-02-28

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.