公开(公告)号：US20250103129A1

公开(公告)日：2025-03-27

申请号：US18474400

申请日：2023-09-26

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar ,  Vivek Asthana ,  Andrew John Turner ,  Alex James Waugh

IPC: G06F1/3296 ,  G06F12/0815

Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

公开(公告)号：US12218664B2

公开(公告)日：2025-02-04

申请号：US17076549

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Rajiv Kumar Sisodia

IPC: G11C11/00 ,  G11C11/417 ,  H03K19/00 ,  G06F113/04

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

公开(公告)号：US20240219955A1

公开(公告)日：2024-07-04

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/10 ,  G06F1/06 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US11631439B1

公开(公告)日：2023-04-18

申请号：US17515258

申请日：2021-10-29

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Munish Kumar ,  Andy Wangkun Chen ,  Rajiv Kumar Sisodia

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C5/06

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

公开(公告)号：US20220123751A1

公开(公告)日：2022-04-21

申请号：US17076549

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Rajiv Kumar Sisodia

IPC: H03K19/00 ,  G11C11/417

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

公开(公告)号：US20220122656A1

公开(公告)日：2022-04-21

申请号：US17076540

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G11C11/418

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

公开(公告)号：US11288432B2

公开(公告)日：2022-03-29

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, Jr. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

公开(公告)号：US20220084561A1

公开(公告)日：2022-03-17

申请号：US17019030

申请日：2020-09-11

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony N/A ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C5/14 ,  G11C8/08

Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.

公开(公告)号：US20220077857A1

公开(公告)日：2022-03-10

申请号：US17013199

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H03K19/17736 ,  H03K19/1776

Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.

公开(公告)号：US11170843B2

公开(公告)日：2021-11-09

申请号：US16824663

申请日：2020-03-19

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Ettore Amirante

IPC: G11C8/00 ,  G11C11/4097 ,  G11C5/02 ,  G11C11/408 ,  G11C11/4094

Abstract: Various implementations described herein are related to a device having a bitcell. The device may include horizontal bitlines coupled to the bitcell. The horizontal bitlines may include multiple first read bitlines disposed in a horizontal direction with respect to the bitcell. The device may include vertical bitlines coupled to the bitcell. The vertical bitlines may include multiple second read bitlines disposed in a vertical direction with respect to the bitcell.