Abstract:
A pixel unit of an organic electroluminescent display having a light emitting area and a transparent area is provided. The pixel unit includes a scan line, a data line, a control element electrically connected to the scan line and the data line, a power line electrically connected to the control element and an organic light-emitting diode disposed inside the light emitting area and electrically connected to the power line and the control element. The power line includes a main portion and a plurality of branch portions connected to the main portion. The branch portions are disposed inside the transparent area and electrically independent from the data line. A width of each of the branch portions is identical to a minimum line width of the data line.
Abstract:
A pixel structure, including a data line, a scan line, at least one active device, a first auxiliary electrode, and a light emitting device, is provided. The at least one active device is electrically connected with the data line and the scan line, and each active device includes a gate, a channel layer, a source, and a drain. The first auxiliary electrode is electrically insulated from the active device. The light emitting device is disposed above the first auxiliary electrode, wherein the light emitting device includes a first electrode layer, a light emitting layer, and a second electrode layer. The first electrode layer is electrically connected with the first auxiliary electrode. The light emitting layer is disposed on the first electrode layer. The second electrode layer is disposed on the light emitting layer, wherein the second electrode layer is electrically connected with the active device.
Abstract:
A pixel unit of an organic electroluminescent display having a light emitting area and a transparent area is provided. The pixel unit includes a scan line, a data line, a control element electrically connected to the scan line and the data line, a power line electrically connected to the control element and an organic light-emitting diode disposed inside the light emitting area and electrically connected to the power line and the control element. The power line includes a main portion and a plurality of branch portions connected to the main portion. The branch portions are disposed inside the transparent area and electrically independent from the data line. A width of each of the branch portions is identical to a minimum line width of the data line.
Abstract:
A display panel is provided, which includes a transparent substrate, a first thin film transistor (TFT), a second TFT, a transparent bottom electrode, a capacitance layer, a transparent top electrode, an opposite substrate and a display medium layer. The transparent substrate has a display region and a peripheral region. The display region has sub-pixel regions, and at least one sub-pixel region at least includes a capacitance region and a transistor region. The first and the second TFTs are disposed on the transistor region of the transparent substrate. The transparent bottom electrode, the capacitance layer and the transparent top electrode are sequentially disposed on the capacitance region of transparent substrate, in which the transparent bottom electrode is connected to a source/drain electrode of the first TFT, and the transparent top electrode is connected to a source/drain electrode of the second TFT.
Abstract:
A light-emitting diode display device and a light-emission control method thereof are provided. The light-emitting diode display device includes a timing controller, multiple display pixels, and a scanning circuit. The display pixels form multiple display rows. The scanning circuit generates multiple scan signals and multiple light-emission signals that respectively drive the display rows. During a first data-writing time period of a first frame period, the timing controller provides multiple writing data to be respectively written into the display rows. During a light-emitting time period, the scanning circuit drives each of the light-emission signals to generate multiple pulses periodically according to a set period to drive the corresponding display rows. The light-emitting time period is after the first data-writing time period and before a second data-writing time period of a second frame period ends.
Abstract:
The disclosure provides a multiplexer and a display panel. In the multiplexer, a first and second output ends are respectively connected to a first and second data transmission lines. Control ends of a first and second switches are respectively coupled to a first and second control lines. First ends of the first and second switches are respectively coupled to the first and second output ends. The first data transmission line, the second data transmission line, the first control line, and the second control line extend along a first direction, and the first output end and the second output end are disposed on opposite sides of the first control line.
Abstract:
A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.
Abstract:
A pixel circuit applied to an uLED display including a LED, a first transistor˜a sixth transistor and a capacitor. The LED is coupled between a first voltage and a first node. The first transistor is coupled between the first node and a second node. The second transistor is coupled between the second node and a second voltage lower than the first voltage. The third transistor is coupled between a third voltage and a third node. The fourth transistor is coupled between the third node and a fourth node. The fifth transistor is coupled between the fourth node and a fourth voltage. A terminal of the sixth transistor is coupled to the first node. The capacitor is coupled between the second node and the fourth node. The fourth transistor is controlled by a second control signal. The third transistor, the fifth transistor and the sixth transistor are controlled by a third control signal.
Abstract:
A display device includes a substrate, a first pixel circuit, a second pixel circuit, a third pixel circuit, a protective layer, a first conductive structure, a second conductive structure, a third conductive structure, first light emitting diodes (LEDs), second LEDs and third LEDs. The first pixel circuit, the second pixel circuit and the third pixel circuit are located on the substrate. The second pixel circuit is located between the first pixel circuit and the third pixel circuit. The protective layer covers the first pixel circuit, the second pixel circuit and the third pixel circuit. The first conductive structure is electrically connected to the first pixel circuit through the first opening of the protective layer. The first LEDs are overlapped with the first pixel circuit and the second pixel circuit. The first LEDs are electrically connected to the first conductive structure.
Abstract:
A method for manufacturing a pixel unit includes the following steps. A channel layer is formed. A first pattern layer is formed above the channel layer and includes a scan line and a gate electrode. A second pattern layer is formed above the first pattern layer and includes a data line and a source electrode, where the source electrode is electrically connected to the channel layer. A third pattern layer is formed above the second pattern layer and includes a drain electrode and an auxiliary electrode, where the drain electrode is electrically connected to the channel layer. The auxiliary electrode is electrically connected to the scan line through a first contact hole.