公开(公告)号：US11281592B2

公开(公告)日：2022-03-22

申请号：US16680491

申请日：2019-11-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber

IPC: G06F12/0877 ,  G06F12/06 ,  G11C7/10 ,  G11C8/12 ,  G06F12/02

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

公开(公告)号：US20180114555A1

公开(公告)日：2018-04-26

申请号：US15299709

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC: G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.