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    Matrix multiplication unit with flexible precision operations
    22.
    发明授权
    Matrix multiplication unit with flexible precision operations 有权

    公开(公告)号：US11762658B2

    公开(公告)日：2023-09-19

    申请号：US16581252

    申请日：2019-09-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Michael Mantor ,  Jiasheng Chen ,  Jian Huang

    IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3877 ,  G06F9/544 ,  G06F17/16

    Abstract: A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. The accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.

    Dedicated vector sub-processor system
    23.
    发明授权
    Dedicated vector sub-processor system 有权

    公开(公告)号：US11630667B2

    公开(公告)日：2023-04-18

    申请号：US16697660

    申请日：2019-11-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Jiasheng Chen ,  Bin He ,  Jian Huang ,  Michael Mantor

    IPC: G06F9/30 ,  G06F9/48

    Abstract: A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.

    Stream processor with decoupled crossbar for cross lane operations
    25.
    发明授权
    Stream processor with decoupled crossbar for cross lane operations 有权

    公开(公告)号：US10970081B2

    公开(公告)日：2021-04-06

    申请号：US15637629

    申请日：2017-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Bin He ,  Mohammad Reza Hakami ,  Timothy Lottes ,  Justin David Smith ,  Michael J. Mantor ,  Derek Carson

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

    Abstract: Systems, apparatuses, and methods for implementing a decoupled crossbar for a stream processor are disclosed. In one embodiment, a system includes at least a multi-lane execution pipeline, a vector register file, and a crossbar. The system is configured to determine if a given instruction in an instruction stream requires a permutation on data operands retrieved from the vector register file. The system conveys the data operands to the multi-lane execution pipeline on a first path which includes the crossbar responsive to determining the given instruction requires a permutation on the data operands. The crossbar then performs the necessary permutation to route the data operands to the proper processing lanes. Otherwise, the system conveys the data operands to the multi-lane execution pipeline on a second path which bypasses the crossbar responsive to determining the given instruction does not require a permutation on the input operands.

    Processor support for bypassing vector source operands
    26.
    发明授权
    Processor support for bypassing vector source operands 有权

    公开(公告)号：US10817302B2

    公开(公告)日：2020-10-27

    申请号：US15644045

    申请日：2017-07-07

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Bin He ,  Mark M. Leather ,  Michael J. Mantor ,  Yunxiao Zou

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0891 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121 ,  G06F12/0875

    Abstract: Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

    STREAM PROCESSOR WITH DECOUPLED CROSSBAR FOR CROSS LANE OPERATIONS
    28.
    发明申请
    STREAM PROCESSOR WITH DECOUPLED CROSSBAR FOR CROSS LANE OPERATIONS 审中-公开

    公开(公告)号：US20190004814A1

    公开(公告)日：2019-01-03

    申请号：US15637629

    申请日：2017-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Bin He ,  Mohammad Reza Hakami ,  Timothy Lottes ,  Justin David Smith ,  Michael J. Mantor ,  Derek Carson

    IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

    Abstract: Systems, apparatuses, and methods for implementing a decoupled crossbar for a stream processor are disclosed. In one embodiment, a system includes at least a multi-lane execution pipeline, a vector register file, and a crossbar. The system is configured to determine if a given instruction in an instruction stream requires a permutation on data operands retrieved from the vector register file. The system conveys the data operands to the multi-lane execution pipeline on a first path which includes the crossbar responsive to determining the given instruction requires a permutation on the data operands. The crossbar then performs the necessary permutation to route the data operands to the proper processing lanes. Otherwise, the system conveys the data operands to the multi-lane execution pipeline on a second path which bypasses the crossbar responsive to determining the given instruction does not require a permutation on the input operands.

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