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公开(公告)号：US12067401B2
公开(公告)日：2024-08-20
申请号：US15855637
申请日：2017-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Yunxiao Zou , Michael J. Mantor , Allen Rush
CPC classification number: G06F9/3867 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F17/16
Abstract: Systems, apparatuses, and methods for implementing a low power parallel matrix multiply pipeline are disclosed. In one embodiment, a system includes at least first and second vector register files coupled to a matrix multiply pipeline. The matrix multiply pipeline comprises a plurality of dot product units. The dot product units are configured to calculate dot or outer products for first and second sets of operands retrieved from the first vector register file. The results of the dot or outer product operations are written back to the second vector register file. The second vector register file provides the results from the previous dot or outer product operations as inputs to subsequent dot or outer product operations. The dot product units receive the results from previous phases of the matrix multiply operation and accumulate these previous dot or outer product results with the current dot or outer product results.
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公开(公告)号：US11880683B2
公开(公告)日：2024-01-23
申请号：US15799560
申请日：2017-10-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Bin He , Yunxiao Zou , Michael J. Mantor , Radhakrishna Giduthuri , Eric J. Finger , Brian D. Emberling
CPC classification number: G06F9/30014 , G06F7/483 , G06F7/57 , G06F9/30036 , G06F9/30112 , G06F2207/3812 , G06F2207/3828
Abstract: Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.
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公开(公告)号：US20210201439A1
公开(公告)日：2021-07-01
申请号：US17181300
申请日：2021-02-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.
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公开(公告)号：US20180357064A1
公开(公告)日：2018-12-13
申请号：US15644045
申请日：2017-07-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Bin He , Mark M. Leather , Michael J. Mantor , Yunxiao Zou
IPC: G06F9/38 , G06F9/30 , G06F12/0875 , G06F12/0891
CPC classification number: G06F9/3867 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/3012 , G06F9/30141 , G06F9/3802 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3857 , G06F12/0804 , G06F12/0855 , G06F12/0875 , G06F12/0891 , G06F12/121 , G06F2212/1008 , G06F2212/1024 , G06F2212/452
Abstract: Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.
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公开(公告)号：US11789732B2
公开(公告)日：2023-10-17
申请号：US17574026
申请日：2022-01-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Bin He , Jiasheng Chen , Jian Huang
CPC classification number: G06F9/3001 , G06F7/57 , G06F9/3009 , G06F9/30101 , G06F9/4806
Abstract: A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double precision operations, the GPU stores the corresponding operands at the operand registers. Over a plurality of execution cycles, the GPU sequences transfer of operands from the set of operand registers to a designated double precision operand register. During each execution cycle, the double-precision ALU executes a double precision operation using the operand stored at the double precision operand register.
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Patent Agency Ranking
公开(公告)号：US10929944B2
公开(公告)日：2021-02-23
申请号：US15360057
申请日：2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.
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公开(公告)号：US20200272687A1
公开(公告)日：2020-08-27
申请号：US16287013
申请日：2019-02-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Qingcheng Wang , Yunxiao Zou
Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.
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公开(公告)号：US20180144435A1
公开(公告)日：2018-05-24
申请号：US15360057
申请日：2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
CPC classification number: G06T1/20 , G06F9/3887 , G06F9/542 , G06F2009/3883 , G06F2209/548 , G06T1/60
Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.
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公开(公告)号：US11409536B2
公开(公告)日：2022-08-09
申请号：US15342809
申请日：2016-11-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Bin He , YunXiao Zou , Jiasheng Chen , Michael Mantor
Abstract: A method and apparatus for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs) includes pairing a first Single Instruction/Multiple Data (SIMD) block channel device with a second SIMD block channel device to create a first block pair having one-level staggering between the first and second channel devices. A third SIMD block channel device is paired with a fourth SIMD block channel device to create a second block pair having one-level staggering between the third and fourth channel devices. A plurality of source inputs are received at the first block pair and the second block pair. The first block pair computes a first result, and the second block pair computes a second result.
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公开(公告)号：US11347827B2
公开(公告)日：2022-05-31
申请号：US16287013
申请日：2019-02-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Qingcheng Wang , Yunxiao Zou
Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.
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