公开(公告)号：US20230097097A1

公开(公告)日：2023-03-30

申请号：US17489105

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey ,  Michael J. Mantor ,  Christopher J. Brennan ,  Mark M. Leather ,  Ryan James Cash

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

公开(公告)号：US12169896B2

公开(公告)日：2024-12-17

申请号：US17489105

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey ,  Michael J. Mantor ,  Christopher J. Brennan ,  Mark M. Leather ,  Ryan James Cash

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

公开(公告)号：US10817302B2

公开(公告)日：2020-10-27

申请号：US15644045

申请日：2017-07-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Jiasheng Chen ,  Bin He ,  Mark M. Leather ,  Michael J. Mantor ,  Yunxiao Zou

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0891 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

公开(公告)号：US20180357064A1

公开(公告)日：2018-12-13

申请号：US15644045

申请日：2017-07-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Jiasheng Chen ,  Bin He ,  Mark M. Leather ,  Michael J. Mantor ,  Yunxiao Zou

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0891

CPC classification number: G06F9/3867 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/3802 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/121 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/452

Abstract: Systems, apparatuses, and methods for implementing a high bandwidth, low power vector register file for use by a parallel processor are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of processing pipeline. The parallel processing unit includes a vector arithmetic logic unit and a high bandwidth, low power, vector register file. The vector register file includes multi-bank high density random-access memories (RAMs) to satisfy register bandwidth requirements. The parallel processing unit also includes an instruction request queue and an instruction operand buffer to provide enough local bandwidth for VALU instructions and vector I/O instructions. Also, the parallel processing unit is configured to leverage the RAM's output flops as a last level cache to reduce duplicate operand requests between multiple instructions. The parallel processing unit includes a vector destination cache to provide additional R/W bandwidth for the vector register file.

公开(公告)号：US20180239606A1

公开(公告)日：2018-08-23

申请号：US15439540

申请日：2017-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Mantor ,  Brian D. Emberling ,  Mark Fowler ,  Mark M. Leather

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for processing variable wavefront sizes on a processor are disclosed. In one embodiment, a processor includes at least a scheduler, cache, and multiple execution units. When operating in a first mode, the processor executes the same instruction on multiple portions of a wavefront before proceeding to the next instruction of the shader program. When operating in a second mode, the processor executes a set of instructions on a first portion of a wavefront. In the second mode, when the processor finishes executing the set of instructions on the first portion of the wavefront, the processor executes the set of instructions on a second portion of the wavefront, and so on until all portions of the wavefront have been processed. The processor determines the operating mode based on one or more conditions.

公开(公告)号：US10474468B2

公开(公告)日：2019-11-12

申请号：US15439540

申请日：2017-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Mantor ,  Brian D. Emberling ,  Mark Fowler ,  Mark M. Leather

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for processing variable wavefront sizes on a processor are disclosed. In one embodiment, a processor includes at least a scheduler, cache, and multiple execution units. When operating in a first mode, the processor executes the same instruction on multiple portions of a wavefront before proceeding to the next instruction of the shader program. When operating in a second mode, the processor executes a set of instructions on a first portion of a wavefront. In the second mode, when the processor finishes executing the set of instructions on the first portion of the wavefront, the processor executes the set of instructions on a second portion of the wavefront, and so on until all portions of the wavefront have been processed. The processor determines the operating mode based on one or more conditions.