公开(公告)号：US07646059B2

公开(公告)日：2010-01-12

申请号：US11501715

申请日：2006-08-10

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US20070040216A1

公开(公告)日：2007-02-22

申请号：US11505337

申请日：2006-08-17

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L29/76

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US20100096696A1

公开(公告)日：2010-04-22

申请号：US12645072

申请日：2009-12-22

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US07692242B2

公开(公告)日：2010-04-06

申请号：US11505337

申请日：2006-08-17

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L29/04 ,  H01L29/06

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US20100006936A1

公开(公告)日：2010-01-14

申请号：US12476147

申请日：2009-06-01

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US07589389B2

公开(公告)日：2009-09-15

申请号：US12264580

申请日：2008-11-04

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

公开(公告)号：US07473978B2

公开(公告)日：2009-01-06

申请号：US11502387

申请日：2006-08-11

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

摘要翻译： 一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

公开(公告)号：US20070034985A1

公开(公告)日：2007-02-15

申请号：US11502387

申请日：2006-08-11

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

摘要翻译： 一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

公开(公告)号：US08981473B2

公开(公告)日：2015-03-17

申请号：US13410739

申请日：2012-03-02

申请人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。

公开(公告)号：US20130049111A1

公开(公告)日：2013-02-28

申请号：US13410739

申请日：2012-03-02

申请人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。