利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.034 秒)

    Semiconductor memory device
    21.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06600672B2

    公开(公告)日：2003-07-29

    申请号：US09963828

    申请日：2001-09-25

    申请人： Mitsuaki Hayashi

    发明人： Mitsuaki Hayashi

    IPC分类号： G11C1700

    CPC分类号： G11C17/12

    摘要： A semiconductor memory device capable of reading out data at a higher speed and occupying a decreased chip-area is provided. The device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines according to a plurality of column selection signals generated based on address signals, a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively, and a bit line grounding circuit including a plurality of third transistors for connecting the plurality of bit lines with a ground potential. This enables the decrease in a charging time during a bit line precharging operation and a discharging time during data reading-out operation. Further, by grounding adjacent bit lines that are not involved in a precharging or reading-out operation so that they have a ground potential, it is also possible to minimize bit line intervals without causing a malfunction due to an increase in capacitances between the bit lines.

    Apparatus on which fan can be mounted
    22.
    发明授权
    Apparatus on which fan can be mounted 有权
    可安装风扇的装置

    公开(公告)号：US08840453B2

    公开(公告)日：2014-09-23

    申请号：US13297512

    申请日：2011-11-16

    申请人： Takaharu Izuno ,  Mitsuaki Hayashi ,  Kenji Joko ,  Osamu Saito ,  Minoru Fujii

    发明人： Takaharu Izuno ,  Mitsuaki Hayashi ,  Kenji Joko ,  Osamu Saito ,  Minoru Fujii

    IPC分类号： H05K5/00 ,  G06F1/20 ,  H05K7/20

    CPC分类号： H05K7/20727

    摘要： An apparatus on which a fan can be mounted, including a casing; a plurality of cooling fan units arranged in line on a lower portion of the casing and capable of being inserted into and removed from the casing on an individual basis; and a plurality of plate members disposed above the line in which the cooling fan units are arranged and above a gap between the cooling fan units, the plate members extending in a direction to which an upper surface of each of the cooling fan units is substantially perpendicular and in which the cooling fan unit is inserted into and removed from the casing, wherein each of the plate members is supported so as to be able to pivot about its lower end portion toward both directions.

    摘要翻译： 一种可安装风扇的装置，包括壳体; 多个冷却风扇单元，其排列在所述壳体的下部并且能够单独地插入到所述壳体中并从壳体中移除; 以及多个板构件，其设置在所述冷却风扇单元布置在所述冷却风扇单元的上方的上方，并且位于所述冷却风扇单元之间的间隙之上，所述板构件沿着每个所述冷却风扇单元的上表面基本垂直的方向延伸 并且其中冷却风扇单元插入到壳体中并从壳体中移除，其中每个板构件被支撑成能够使其下端部朝向两个方向枢转。

    PLUG-IN UNIT
    23.
    发明申请
    PLUG-IN UNIT 有权
    插入式单元

    公开(公告)号：US20130003327A1

    公开(公告)日：2013-01-03

    申请号：US13449926

    申请日：2012-04-18

    申请人： Osamu Saito ,  Hideaki Matsumoto ,  Mitsuaki Hayashi ,  Kenji Joko ,  Minoru Fujii ,  Takaharu Izuno

    发明人： Osamu Saito ,  Hideaki Matsumoto ,  Mitsuaki Hayashi ,  Kenji Joko ,  Minoru Fujii ,  Takaharu Izuno

    IPC分类号： H05K5/00

    CPC分类号： H05K7/1461

    摘要： A plug-in unit includes: a printed circuit board on which a connector is mounted; and a cover in which the printed circuit board is accommodated; wherein the cover allows the connector to be exposed when the plug-in unit is inserted into a housing and to be covered when the plug-in unit is in a standalone state in which the plug-in unit is not inserted into the housing.

    摘要翻译： 插入单元包括：安装有连接器的印刷电路板; 以及容纳印刷电路板的盖子; 其中当所述插入单元插入到壳体中时，所述盖允许所述连接器暴露，并且当所述插入单元处于所述插入单元未插入所述壳体的独立状态时被覆盖。

    Semiconductor memory device
    25.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07554868B2

    公开(公告)日：2009-06-30

    申请号：US11846634

    申请日：2007-08-29

    申请人： Mitsuaki Hayashi

    发明人： Mitsuaki Hayashi

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C8/10

    摘要： A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed during manufacture are eliminated. The semiconductor memory device is provided with word line selection circuits connected with a row address signal line to select some desired word line according to an address input and dummy word line potential fixation circuits connected to word lines for dummy memory cells. As in the case of the word line selection circuits, the dummy word line potential fixation circuits each include a NAND gate NANDR(i) (i=−1, 0, m+1, or m+2) and an inverter INVR(i) (i=−1, 0, m+1, or m+2). The inputs of the dummy word line potential fixation circuits are connected with a row address signal line such that the word lines for the dummy memory cells are maintained in a non-selected state at all times. These make it possible to make the circuits which selectively drive all the word lines identical with each other in configuration, reduce the area of the row selection circuit, and eliminate the effects of exposure, etching, and so on during manufacture.

    摘要翻译： 实现了半导体存储单元，其中行选择电路的面积减小，并且消除了在制造期间执行的曝光，蚀刻等的影响。 半导体存储器件具有与行地址信号线连接的字线选择电路，以根据地址输入选择一些期望的字线，以及连接到虚拟存储器单元的字线的虚拟字线电位固定电路。 如字线选择电路的情况，虚拟字线电位固定电路各自包括与非门NANDR（i）（i = -1,0，m + 1或m + 2）和反相器INVR（i ）（i = -1,0，m + 1或m + 2）。 虚拟字线电位固定电路的输入与行地址信号线连接，使得虚拟存储单元的字线始终保持在非选择状态。 这些使得可以使构成中选择性地驱动所有字线彼此相同的电路成为可能，减少了行选择电路的面积，并且消除了在制造期间的曝光，蚀刻等的影响。

    Process for producing olefin by catalytic cracking of hydrocarbon
    26.
    发明授权
    Process for producing olefin by catalytic cracking of hydrocarbon 失效
    通过烃的催化裂化生产烯烃的方法

    公开(公告)号：US07531706B2

    公开(公告)日：2009-05-12

    申请号：US10532097

    申请日：2003-10-21

    申请人： Kenichi Wakui ,  Yoshihiro Nakamura ,  Mitsuaki Hayashi

    发明人： Kenichi Wakui ,  Yoshihiro Nakamura ,  Mitsuaki Hayashi

    IPC分类号： C07C4/06 ,  C10C11/05 ,  B01J29/06

    CPC分类号： B01J29/48 ,  B01J29/405 ,  C07C4/06 ,  C07C2529/48 ,  C10G2400/20 ,  C07C11/02

    摘要： A process for producing olefin by catalytic cracking of hydrocarbon material characterized in employing zeolite of penta-sil type comprising rare earth elements and at least one of manganese or zirconium as a catalyst. It enables to produce light olefin such as ethylene, propylene, and so on with selectively high yield and with long term stability, by catalytic cracking of gaseous or liquid hydrocarbon as ingredients under lower temperature than the conventional method and suppressing by-product such as aromatic hydrocarbon or heavy substances.

    摘要翻译： 一种通过烃材料的催化裂化生产烯烃的方法，其特征在于使用包含稀土元素和至少一种锰或锆作为催化剂的五硅型沸石。 通过在比常规方法更低的温度下作为成分的气态或液态烃的催化裂化，能够选择性地高产率和长期稳定性，生产轻质烯烃如乙烯，丙烯等，并抑制副产物如芳族化合物 烃类或重物质。

    SEMICONDUCTOR DEVICE FOR OUTPUTTING DATA READ FROM A READ ONLY STORAGE DEVICE
    27.
    发明申请
    SEMICONDUCTOR DEVICE FOR OUTPUTTING DATA READ FROM A READ ONLY STORAGE DEVICE 有权
    用于从只读存储器件输出数据的半导体器件

    公开(公告)号：US20070133324A1

    公开(公告)日：2007-06-14

    申请号：US11674184

    申请日：2007-02-13

    申请人： Shuji Nakaya ,  Mitsuaki Hayashi

    发明人： Shuji Nakaya ,  Mitsuaki Hayashi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/846 ,  G11C29/785

    摘要： A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal. The switching circuit inputs the controlling signal and data outputted from a read only storage device which is selected by an address signal and outputs the data from the read only storage device. The switching circuit inverts a defective bit of the data outputted from the read only storage device in response to receipt of the controlling signal from the bit storage circuit and outputs data whose defective bit is inverted instead of the data outputted from the read only storage device.

    摘要翻译： 提供半导体器件用于输出从只读存储器读取的数据。 半导体器件包括只读存储器件，包括存储器单元，用于向每个只读存储器件发送地址信号的地址信号线，以及输入地址信号的开关器件。 地址信号表示存储要读取的数据的存储单元的地址。 开关装置包括地址存储电路，位存储电路和开关存储电路。 地址存储电路存储只读存储装置的缺陷存储单元的地址信息，并且检测存储由地址信号选择的数据的存储单元是否包含有缺陷的存储单元。 位存储电路存储指示存储在包括有缺陷存储单元的存储单元中的数据的哪一位的位信息，并输出控制信号。 切换电路输入从地址信号选择的只读存储装置输出的控制信号和数据，并从只读存储装置输出数据。 开关电路响应于来自位存储电路的控制信号的接收而反转从只读存储装置输出的数据的有缺陷的位，并且输出其缺陷位被反相的数据，而不是从只读存储装置输出的数据。

    Semiconductor memory device
    28.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060158942A1

    公开(公告)日：2006-07-20

    申请号：US11151639

    申请日：2005-06-14

    申请人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

    发明人： Mitsuaki Hayashi ,  Wataru Abe ,  Shuji Nakaya ,  Masakazu Kurata

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C17/12

    摘要： A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

    摘要翻译： 半导体存储器件包括存储单元阵列，补偿在所选位线产生的OFF漏电流的充电电路，具有对应于未选择位线上的电位的接地电位的复位电路，由多个位线组成的读电路 的栅极连接到位线的晶体管，以及位线预充电电路，其对所选择的位线进行固定时间段的充电。 作为采用这种结构的结果，不需要在读取电路和位线之间的充电路径上提供诸如列解码器的传输门，使得可以实现低电源电压操作 而不受衬底偏置效应的影响。