公开(公告)号：US20110007595A1

公开(公告)日：2011-01-13

申请号：US12888158

申请日：2010-09-22

申请人： Yasuhiro AGATA ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

发明人： Yasuhiro AGATA ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

IPC分类号： G11C17/16

CPC分类号： G11C11/4072 ,  G11C17/165 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5002

摘要： An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

摘要翻译： 电子设备系统包括：半导体集成电路，具有存储有关半导体集成电路的特性的信息的非易失性存储器; 以及控制器，被配置为控制半导体集成电路。 控制器具有基于存储在非易失性存储器中的信息调整对半导体集成电路的访问参数的功能。

公开(公告)号：US08072832B2

公开(公告)日：2011-12-06

申请号：US12888158

申请日：2010-09-22

申请人： Yasuhiro Agata ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

发明人： Yasuhiro Agata ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

IPC分类号： G11C17/16

CPC分类号： G11C11/4072 ,  G11C17/165 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5002

摘要： An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

摘要翻译： 电子设备系统包括：半导体集成电路，具有存储有关半导体集成电路的特性的信息的非易失性存储器; 以及控制器，被配置为控制半导体集成电路。 控制器具有基于存储在非易失性存储器中的信息调整对半导体集成电路的访问参数的功能。

公开(公告)号：US20090180306A1

公开(公告)日：2009-07-16

申请号：US12243299

申请日：2008-10-01

申请人： Yutaka Terada ,  Yasuhiro Agata ,  Wataru Abe ,  Masakazu Kurata ,  Kenji Misumi

发明人： Yutaka Terada ,  Yasuhiro Agata ,  Wataru Abe ,  Masakazu Kurata ,  Kenji Misumi

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  H01L27/0207 ,  H01L27/112 ,  H01L27/11253

摘要： A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

摘要翻译： 分割存储器阵列的末端列上的电路由具有与存储单元晶体管相同形状的块选择晶体管形成。 由于主位线和子位线之间的连接部分的图形与存储单元的形状相同，所以可以实现图案均匀性，并且不需要使用存储器阵列虚拟图案 。

公开(公告)号：US20110141825A1

公开(公告)日：2011-06-16

申请号：US13036327

申请日：2011-02-28

申请人： Ichiro Hatanaka ,  Kenji Misumi ,  Tomoyuki Aihara ,  Masanori Shirahama

发明人： Ichiro Hatanaka ,  Kenji Misumi ,  Tomoyuki Aihara ,  Masanori Shirahama

IPC分类号： G11C7/00 ,  G11C5/14 ,  G06F1/04

CPC分类号： G11C11/417 ,  G11C11/41 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/5006

摘要： A semiconductor integrated circuit system comprises a semiconductor memory device including a memory cell array having a plurality of memory cells; a monitor circuit for monitoring characteristics of the memory cells; and a voltage output circuit connected to the semiconductor memory device to supply a power supply voltage to the semiconductor memory device; the voltage output circuit being configured to change an output voltage according to an output of the monitor circuit.

摘要翻译： 半导体集成电路系统包括具有多个存储单元的存储单元阵列的半导体存储器件; 用于监视存储器单元的特性的监视器电路; 以及电压输出电路，连接到半导体存储器件，以向半导体存储器件提供电源电压; 电压输出电路被配置为根据监视电路的输出来改变输出电压。

公开(公告)号：US07280409B2

公开(公告)日：2007-10-09

申请号：US11377433

申请日：2006-03-17

申请人： Kenji Misumi ,  Makoto Kojima

发明人： Kenji Misumi ,  Makoto Kojima

IPC分类号： G11C11/34

CPC分类号： G11C16/102 ,  G11C16/30

摘要： Even when the number of rewrite operations varies among erase unit areas, the number of rewrite operations is improved for all of the erase unit areas. A flash EEPROM 100 comprises a trimming value storing area 130 of storing a trimming value corresponding to each erase unit area 120 included in a memory cell array 110. When an erase operation and a write operation are performed with respect to a certain erase unit area 120, a regulator circuit 150 converts a voltage boosted by a booster circuit 140 to a level corresponding to the trimming value for the erase unit area 120. When a read determination circuit 170 detects an abnormality as the number of rewrite operations is increased, the trimming value is updated to a value which causes the regulator circuit 150 to increase the output voltage.

摘要翻译： 即使重写操作的数量在擦除单元区域之间变化，对于所有的擦除单元区域也改善了重写操作的数量。 闪存EEPROM 100包括修整值存储区域130，其存储对应于包括在存储单元阵列110中的每个擦除单元区域120的修整值。 当相对于某个擦除单元区域120执行擦除操作和写入操作时，调节器电路150将由升压电路140升压的电压转换为与擦除单元区域120的修整值相对应的电平。 当读取确定电路170随着重写操作数量的增加而检测到异常时，修整值被更新为使调节器电路150增加输出电压的值。

公开(公告)号：US07248503B2

公开(公告)日：2007-07-24

申请号：US11242894

申请日：2005-10-05

申请人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

发明人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

摘要翻译： 提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。 提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

公开(公告)号：US20070165460A1

公开(公告)日：2007-07-19

申请号：US11633586

申请日：2006-12-05

申请人： Masahiro Toki ,  Hiroyasu Nagai ,  Kenji Misumi ,  Hideto Kotani

发明人： Masahiro Toki ,  Hiroyasu Nagai ,  Kenji Misumi ,  Hideto Kotani

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/0466 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/16

摘要： In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial variation (charge loss phenomenon caused by binding of injected charge with the surrounding charge in an extremely short time) occurring immediately after programming. Thereafter, the charge loss in the initial variation is compensated, so that the subsequent data retention characteristic is improved. The second charge injection is executed only when a predetermined determination level has been reached.

摘要翻译： 在具有陷阱层的非易失性存储单元中，通过在编程或擦除顺序中以给定的等待时间执行第一次充电注入和第一次充电注入之后的第二次充电注入，利用可能劣化数据保持特性的周围电荷来利用 在编程之后立即出现初始变化（由注入的电荷与极短时间内的周围电荷的结合引起的电荷损失现象）。 此后，补偿初始变化中的电荷损失，从而提高随后的数据保持特性。 仅在已经达到预定的确定水平时执行第二次充电注入。

公开(公告)号：US06999349B2

公开(公告)日：2006-02-14

申请号：US10781808

申请日：2004-02-20

申请人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

发明人： Kenji Misumi ,  Atsushi Fujiwara ,  Masanori Matsuura ,  Toshio Nishimoto

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

摘要翻译： 提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。 提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

公开(公告)号：US20090034340A1

公开(公告)日：2009-02-05

申请号：US12182782

申请日：2008-07-30

申请人： Kenji Misumi

发明人： Kenji Misumi

IPC分类号： G11C16/10

CPC分类号： G06F13/16 ,  G11C16/10

摘要： A memory controller outputs an additional writing instruction to one of a plurality of non-volatile memories arbitrarily selected via a writing instruction output unit when a signal which rejects a writing operation is not outputted from writing controllers of the plurality of non-volatile memories for a certain period of time, and outputs a temporary writing instruction to another non-volatile memory at least once via the writing instruction output unit by the time when the additional writing operation is completed in the arbitrary non-volatile memory.

摘要翻译： 当禁止写入操作的信号不从多个非易失性存储器的写入控制器输出时，存储器控制器向经由写入指令输出单元任意选择的多个非易失性存储器之一输出附加写入指令， 并且在任意非易失性存储器中的附加写入操作完成时，经由写入指令输出单元至少一次向另一个非易失性存储器输出临时写入指令。

公开(公告)号：US20070047318A1

公开(公告)日：2007-03-01

申请号：US11502430

申请日：2006-08-11

申请人： Hiroyasu Nagai ,  Masahiro Toki ,  Kenji Misumi ,  Hideto Kotani

发明人： Hiroyasu Nagai ,  Masahiro Toki ,  Kenji Misumi ,  Hideto Kotani

IPC分类号： G11C16/04

CPC分类号： G11C16/349

摘要： In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

摘要翻译： 在具有陷阱层的非易失性存储单元中，按照第一次电荷注入的顺序进行编程或擦除，同时确保给定的等待时间，并且在第一次电荷注入之后执行第二次电荷注入。 通过使用编程后立即发生的初始变化（由于注入的电荷与周围电荷的结合在极短的时间内导致的电荷损失现象），从而降低数据保持特性的周围电荷，然后由于初始变化引起的电荷损失 被补偿，从而提高数据保持特性。