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公开(公告)号：US20190042795A1
公开(公告)日：2019-02-07
申请号：US16022402
申请日：2018-06-28
申请人： Anatoli Bolotov , Mikhail Grinchuk
发明人： Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G06F21/64 , G06F11/10 , G11C29/52 , G06F12/0815 , H04L9/08
摘要： System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter in the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.
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公开(公告)号：US08654969B2
公开(公告)日：2014-02-18
申请号：US12673022
申请日：2009-04-10
CPC分类号： G06F21/602 , G09C1/00 , H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.
摘要翻译： 公开了一种密码独立的密码硬件服务。 密码独立事务被接收到输入时隙（202）中。 输入插槽包含用于保存事务的FIFO。 这些事务从密码独立形式转换为密码依赖格式（206），并将它们从FIFO中删除。 在通过密码特定硬件的密码处理之后，将结果发送到输出FIFO（212）。 可以使用多个FIFO和加密硬件，使得可以并行并且同时执行多个加密功能。
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公开(公告)号：US08650146B2
公开(公告)日：2014-02-11
申请号：US12822349
申请日：2010-06-24
IPC分类号： G06N5/02
CPC分类号： G06N5/022 , G06F7/02 , G06F17/30985 , G06F2207/025 , G06N5/047
摘要： Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.
摘要翻译： 公开了一种用于匹配正则表达式的方法和装置。 维持每个符号的最后出现位置数的符号缓冲器。 当两个常数在正则表达式运算符的任一侧匹配时，查询符号缓冲区以确定正则表达式运算符的补码的成员是否在两个常量之间发生。 如果是这样，那么操作员不满意。 如果没有，那么操作员就满意了。
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公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译： 一种包括第一电路和第二电路的存储器环。 第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。 在测试模式期间，可以将一个或多个数据序列呈现给存储器。 第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。
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公开(公告)号：US20090300441A1
公开(公告)日：2009-12-03
申请号：US12183562
申请日：2008-07-31
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译： 存储器环包括第一电路，第二电路和第三电路。 第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。 第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。 第三电路可以被配置为生成一个或多个地址序列。 在测试模式期间将一个或多个地址序列呈现给存储器。
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公开(公告)号：US20060129874A1
公开(公告)日：2006-06-15
申请号：US10999720
申请日：2004-11-30
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译： 用于RRAM子系统的主控制器。 接口与至少一个RRAM控制器通信。 主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。 定时器确定在给定时间内可以实现的最大测试和修复操作数。 因此，主控制器包含在RRAM子系统中。 主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。 使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。 以这种方式，RRAM子系统具有自修复功能。
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公开(公告)号：US20110255689A1
公开(公告)日：2011-10-20
申请号：US12761024
申请日：2010-04-15
IPC分类号： H04L9/18
CPC分类号： H04L9/0637 , H04L9/0631 , H04L2209/04 , H04L2209/125
摘要： In one embodiment, a multi-mode Advanced Encryption Standard (MM-AES) module for a storage controller is adapted to perform interleaved processing of multiple data streams, i.e., concurrently encrypt and/or decrypt string-data blocks from multiple data streams using, for each data stream, a corresponding cipher mode that is any one of a plurality of AES cipher modes. The MM-AES module receives a string-data block with (a) a corresponding key identifier that identifies the corresponding module-cached key and (b) a corresponding control command that indicates to the MM-AES module what AES-mode-related processing steps to perform on the data block. The MM-AES module generates, updates, and caches masks to preserve inter-block information and allow the interleaved processing. The MM-AES module uses an unrolled and pipelined architecture where each processed data block moves through its processing pipeline in step with correspondingly moving key, auxiliary data, and instructions in parallel pipelines.
摘要翻译： 在一个实施例中，用于存储控制器的多模式高级加密标准（MM-AES）模块适于执行多个数据流的交织处理，即，从多个数据流同时加密和/或解密串数据块， 对于每个数据流，具有作为多个AES密码模式中的任何一个的对应密码模式。 MM-AES模块接收一个字符串数据块，其中（a）标识对应的模块缓存密钥的对应的密钥标识符和（b）相应的控制命令，指示MM-AES模块与AES模式相关的处理 在数据块上执行的步骤。 MM-AES模块生成，更新和缓存掩码以保留块间信息并允许交错处理。 MM-AES模块使用展开和流水线架构，其中每个处理的数据块通过相应的移动键，辅助数据和并行管道中的指令一步一步地移动通过其处理流水线。
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公开(公告)号：US07949909B2
公开(公告)日：2011-05-24
申请号：US12183562
申请日：2008-07-31
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译： 存储器环包括第一电路，第二电路和第三电路。 第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。 第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。 第三电路可以被配置为生成一个或多个地址序列。 在测试模式期间将一个或多个地址序列呈现给存储器。
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公开(公告)号：US07890565B2
公开(公告)日：2011-02-15
申请号：US11741865
申请日：2007-04-30
IPC分类号： G06F7/72
CPC分类号： G06F7/724 , H04L9/0631 , H04L2209/122 , H04L2209/125
摘要： A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).
摘要翻译： 不常称之为微小乘法单元和基于已知Tn快速计算T（n + 1）的“差分”单元的组合。 调度（调用乘法单元的频率）可以被认为是算法的参数。 所提出的“差分”单元的架构在速度（延迟）和面积（门数）方面都是有效的。
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公开(公告)号：US20100086127A1
公开(公告)日：2010-04-08
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译： 一种包括初始化电路和散列计算电路的装置。 初始化电路可以被配置为呈现多个初始化值。 哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。 哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。
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