CONFIGURABLE LOGIC PLATFORM
    21.
    发明申请

    公开(公告)号:US20230018032A1

    公开(公告)日:2023-01-19

    申请号:US17952144

    申请日:2022-09-23

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Adaptive use of search modes based on bandwidth availability

    公开(公告)号:US10694189B1

    公开(公告)日:2020-06-23

    申请号:US16357120

    申请日:2019-03-18

    Abstract: Reference data is one type of data that the video accelerator may frequently be read from external memory. In various examples, the video accelerator can adaptively select inter-prediction modes based on the bandwidth to external memory that is available at any point in time. The video accelerator can determine the amount of bandwidth that is available, and when the bandwidth is insufficient for obtaining reference data for all possible inter-prediction modes, the video accelerator can select an inter-prediction mode based on the size of the reference window associated with the inter-prediction mode, the size being within an amount of data that can be read with the available bandwidth. The video accelerator can then obtain a reference window from external memory, and perform prediction using the selected inter-prediction mode and the reference window.

    Broadcasting writes to multiple modules

    公开(公告)号:US10185671B1

    公开(公告)日:2019-01-22

    申请号:US14983145

    申请日:2015-12-29

    Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

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