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公开(公告)号：US20250071415A1
公开(公告)日：2025-02-27
申请号：US18943384
申请日：2024-11-11
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Chaminda N. Vidanagamachchi , Yohan Rajan , Anselm Grundhoefer
IPC: H04N23/65 , G06V10/10 , G06V10/147 , G06V10/22 , G06V10/82 , G06V20/52 , G06V20/58 , G08B13/196 , H04N7/18 , H04N23/45 , H04N23/61 , H04N23/667
Abstract: An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.
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公开(公告)号：US12135993B2
公开(公告)日：2024-11-05
申请号：US18321919
申请日：2023-05-23
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Yohan Rajan , Chaminda Nalaka Vidanagamachchi , Anthony Ghannoum
Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.
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公开(公告)号：US20240193810A1
公开(公告)日：2024-06-13
申请号：US18581251
申请日：2024-02-19
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Anthony Ghannoum , Michele Stoppa , Kiranjit Dhaliwal
CPC classification number: G06T7/74 , G06F3/14 , G06T13/00 , H04N23/651 , H04N23/66 , G01S5/02585 , G01S5/16
Abstract: A tracked device may be used in an extended reality system in coordination with a tracking device. The tracked device may be ordinarily difficult to track, for example due to changing appearances or relatively small surface areas of unchanging features, as may be the case with an electronic device with a relatively large display surrounded by a thin physical outer boundary. In these cases, the tracked device may periodically present an image to the tracking device that the tracking device stores as an indication to permit tracking of a known, unchanging feature despite the image not being presented continuously on the display of the tracked device. The image may include a static image, designated tracking data overlaid on an image frame otherwise scheduled for presentation, or extracted image features from the image frame otherwise scheduled for presentation. Additional power saving methods and known marker generation methods are also described.
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Patent Agency Ranking
公开(公告)号：US20240005972A1
公开(公告)日：2024-01-04
申请号：US18346565
申请日：2023-07-03
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Mohamed H. Abu-Rahma , Jelam K. Parekh , Yildiz Sinangil , Mohammad Ghasemzadeh , Anthony Ghannoum , Chaminda N. Vidanagamachchi
CPC classification number: G11C7/222 , H03M1/82 , G11C7/1087 , G11C7/106
Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.
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公开(公告)号：US11693699B2
公开(公告)日：2023-07-04
申请号：US16919930
申请日：2020-07-02
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Yohan Rajan , Chaminda Nalaka Vidanagamachchi , Anthony Ghannoum
CPC classification number: G06F9/5016 , G06F9/3004 , G06F9/5044
Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.
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公开(公告)号：US11593628B2
公开(公告)日：2023-02-28
申请号：US16810675
申请日：2020-03-05
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Waleed Abdulla , Chaminda N. Vidanagamachchi , Yohan Rajan
Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.
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公开(公告)号：US20220004236A1
公开(公告)日：2022-01-06
申请号：US16919908
申请日：2020-07-02
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Yohan Rajan , Chaminda Nalaka Vidanagamachchi
Abstract: In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.
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公开(公告)号：US20210279557A1
公开(公告)日：2021-09-09
申请号：US16810675
申请日：2020-03-05
Applicant: Apple Inc.
Inventor： Paolo Di Febbo , Waleed Abdulla , Chaminda N. Vidanagamachchi , Yohan Rajan
Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.
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