公开(公告)号：US20230059200A1

公开(公告)日：2023-02-23

申请号：US17406817

申请日：2021-08-19

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C7/22 ,  G11C7/10 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US12230361B2

公开(公告)日：2025-02-18

申请号：US18346565

申请日：2023-07-03

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US20240231758A1

公开(公告)日：2024-07-11

申请号：US18417868

申请日：2024-01-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  G06F17/15 ,  G06N20/00 ,  H03M1/46

CPC classification number: G06F7/5443 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46 ,  G06N20/00

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.

公开(公告)号：US11914973B2

公开(公告)日：2024-02-27

申请号：US16953093

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  H03M1/46 ,  G06F17/15 ,  G06N20/00

CPC classification number: G06F7/5443 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46 ,  G06N20/00

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.

公开(公告)号：US20240005972A1

公开(公告)日：2024-01-04

申请号：US18346565

申请日：2023-07-03

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C7/22 ,  H03M1/82 ,  G11C7/10

CPC classification number: G11C7/222 ,  H03M1/82 ,  G11C7/1087 ,  G11C7/106

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US11694733B2

公开(公告)日：2023-07-04

申请号：US17406817

申请日：2021-08-19

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C8/00 ,  G11C7/22 ,  H03M1/82 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1087 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US20220156045A1

公开(公告)日：2022-05-19

申请号：US16953093

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Shahzad Nazar ,  Bharan Giridhar ,  Mohamed H. Abu-Rahma ,  Ajay Bhatia ,  Mayur V. Joshi ,  Yildiz Sinangil ,  Aravind Kandala

IPC: G06F7/544 ,  G06F7/523 ,  G06F17/15 ,  H03M1/46

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.

公开(公告)号：US09786357B2

公开(公告)日：2017-10-10

申请号：US15046329

申请日：2016-02-17

Applicant: Apple Inc.

Inventor： Mohamed H. Abu-Rahma ,  Yildiz Sinangil

IPC: G11C11/00 ,  G11C11/418 ,  G11C8/08

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.

公开(公告)号：US20170236577A1

公开(公告)日：2017-08-17

申请号：US15046329

申请日：2016-02-17

Applicant: Apple Inc.

Inventor： Mohamed H. Abu-Rahma ,  Yildiz Sinangil

IPC: G11C11/418 ,  G11C8/08

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.

公开(公告)号：US10720193B2

公开(公告)日：2020-07-21

申请号：US16147454

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Yildiz Sinangil ,  Mohamed H. Abu-Rahma

IPC: G11C5/14 ,  G11C7/12 ,  G11C5/06 ,  G11C11/419

Abstract: A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.