公开(公告)号：US11770274B1

公开(公告)日：2023-09-26

申请号：US17664747

申请日：2022-05-24

Applicant: Apple Inc.

Inventor： Wing Liu ,  Sanjeev K. Maheshwari

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.

公开(公告)号：US11063600B1

公开(公告)日：2021-07-13

申请号：US16929995

申请日：2020-07-15

Applicant: Apple Inc.

Inventor： Wenbo Liu ,  Wei-Ming Lee ,  Sanjeev K. Maheshwari

IPC: H03L7/099 ,  H03K3/03 ,  H03L7/191

Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.

公开(公告)号：US11023403B2

公开(公告)日：2021-06-01

申请号：US16700356

申请日：2019-12-02

Applicant: Apple Inc.

Inventor： Jafar Savoj ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Brian S. Leibowitz ,  Pradeep R. Trivedi ,  Gin Yee ,  Emerson S. Fang

IPC: G06F13/42 ,  G06F9/52 ,  G06F13/40

Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.