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公开(公告)号：US10734040B1
公开(公告)日：2020-08-04
申请号：US16369395
申请日：2019-03-29
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia
Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.
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公开(公告)号：US10732693B2
公开(公告)日：2020-08-04
申请号：US16379451
申请日：2019-04-09
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Kumar Bhatia
IPC: G05F1/46 , G06F1/3206 , H03K17/62 , H03K17/22 , G06F1/3287 , G06F1/3296 , G06F30/39
Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.
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公开(公告)号：US20190089354A1
公开(公告)日：2019-03-21
申请号：US15710406
申请日：2017-09-20
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Michael R. Seningen , Ajay Bhatia
Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.
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公开(公告)号：US20190089337A1
公开(公告)日：2019-03-21
申请号：US15710526
申请日：2017-09-20
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Michael R Seningen , Ajay Bhatia
IPC: H03K3/037
Abstract: An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.
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公开(公告)号：US11870442B2
公开(公告)日：2024-01-09
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
CPC classification number: H03K3/0372 , G06F1/08 , G06F1/28
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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Patent Agency Ranking
公开(公告)号：US20220345117A1
公开(公告)日：2022-10-27
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US11424734B2
公开(公告)日：2022-08-23
申请号：US17327365
申请日：2021-05-21
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Qi Ye
Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.
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公开(公告)号：US11418174B2
公开(公告)日：2022-08-16
申请号：US17245623
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Greg M. Hess , Vivekanandan Venugopal , Victor Zyuban
Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
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公开(公告)号：US11418173B2
公开(公告)日：2022-08-16
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US11336272B2
公开(公告)日：2022-05-17
申请号：US17028790
申请日：2020-09-22
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Qi Ye
IPC: H03K3/012 , H03K3/356 , H03K3/037 , H03K3/0233
Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.
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