公开(公告)号：US20240012748A1

公开(公告)日：2024-01-11

申请号：US17861084

申请日：2022-07-08

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/1008

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

公开(公告)号：US11688444B2

公开(公告)日：2023-06-27

申请号：US17209876

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Akash Bangalore Srinivasa ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sreebin Sreedhar ,  Balaji Ravikumar ,  Penaka Phani Goberu ,  Vibin Vincent

IPC: G11C8/08 ,  G11C11/16 ,  G11C11/418

CPC classification number: G11C8/08 ,  G11C11/1657 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

公开(公告)号：US11676656B2

公开(公告)日：2023-06-13

申请号：US17168428

申请日：2021-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US20220319585A1

公开(公告)日：2022-10-06

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, JR.

IPC: G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US20220254411A1

公开(公告)日：2022-08-11

申请号：US17168428

申请日：2021-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US11380384B2

公开(公告)日：2022-07-05

申请号：US17006689

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/413

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US20220130816A1

公开(公告)日：2022-04-28

申请号：US17077532

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  H01L25/065 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00 ,  G06F30/31

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US20220122654A1

公开(公告)日：2022-04-21

申请号：US17076305

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony

IPC: G11C11/417 ,  H01L27/11

Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.

公开(公告)号：US11280832B1

公开(公告)日：2022-03-22

申请号：US17013628

申请日：2020-09-06

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Frank David Frederick ,  Richard Slobodnik

IPC: G01R31/3177 ,  G11C11/419 ,  G01R31/317 ,  G11C11/409 ,  H03K19/20

Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.

公开(公告)号：US11200922B2

公开(公告)日：2021-12-14

申请号：US16725779

申请日：2019-12-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Munish Kumar

IPC: G11C7/10 ,  G11C7/22

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.