公开(公告)号：US11307856B2

公开(公告)日：2022-04-19

申请号：US16971755

申请日：2019-02-13

Applicant: Arm Limited

Inventor： Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F9/30 ,  G06F9/32

Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

公开(公告)号：US10719383B2

公开(公告)日：2020-07-21

申请号：US15743392

申请日：2016-06-21

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Michael John Williams ,  Richard Roy Grisenthwaite

IPC: G06F11/00 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

公开(公告)号：US10649787B2

公开(公告)日：2020-05-12

申请号：US15759907

申请日：2016-09-09

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Richard Roy Grisenthwaite

IPC: G06F9/38 ,  G06F9/455 ,  G06F9/30 ,  G06F11/07

Abstract: A data processing system includes exception handling circuitry to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank. Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

公开(公告)号：US20190171573A1

公开(公告)日：2019-06-06

申请号：US15831609

申请日：2017-12-05

Applicant: Arm Limited

Inventor： Andrew Christopher Rose ,  Richard Roy Grisenthwaite ,  Ali Ghassan Saidi

IPC: G06F12/0891 ,  G06F12/126 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.

公开(公告)号：US09727343B2

公开(公告)日：2017-08-08

申请号：US14788848

申请日：2015-07-01

Applicant: ARM Limited

Inventor： Richard Roy Grisenthwaite

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30101 ,  G06F9/30189

Abstract: Processing circuitry has a plurality of exception states for handling exception events, the exception states including a base level exception state and at least one further level exception state. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store. When the processing circuitry is in the base level exception state, stack pointer selection circuitry selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry. When the processing circuitry is a further exception state, the stack pointer selection circuitry selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

公开(公告)号：US09218302B2

公开(公告)日：2015-12-22

申请号：US13926140

申请日：2013-06-25

Applicant: ARM LIMITED

Inventor： Richard Roy Grisenthwaite ,  Matthew Lucien Evans

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F2212/151

Abstract: Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page.

Abstract translation: 存储器地址空间内的每一页的页表数据包括写允许标志和脏位修饰符标志。 写许可标志被初始化为一个值，表示不允许写访问。 当发生写入访问时，脏位修饰符标志指示是否可以覆盖写许可标志的动作。 如果可写入许可标志的动作可能被覆盖，则允许写访问，并改变写允许标志，以指示此后允许写访问。 写权限标志指示允许写入的页面是脏页。

公开(公告)号：US09202071B2

公开(公告)日：2015-12-01

申请号：US13741709

申请日：2013-01-15

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC: G06F21/00 ,  G06F21/60 ,  G06F21/52 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/606 ,  G06F9/3009 ,  G06F9/30101 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/2105

Abstract: A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data.

Abstract translation: 提供了一种用于处理异常的数据处理装置和方法，包括配置为响应于程序代码执行数据处理操作的处理电路，所述电路包括异常控制电路。 提供了多个寄存器，包括第一和第二寄存器子集，以及数据存储器。 数据存储器包括安全区域和较不安全的区域，其中安全区域用于存储当在安全域中操作时由处理电路可访问的数据，并且当在较不安全的域中操作时由处理电路不可访问。 异常控制电路在触发处理电路之前对寄存器的第一子集进行数据的状态保存，以执行与异常相对应的异常处理程序。 在由安全域中的处理电路执行背景处理的情况下，异常控制电路执行数据的附加状态保存。

公开(公告)号：US20240095183A1

公开(公告)日：2024-03-21

申请号：US18263665

申请日：2022-02-02

Applicant: Arm Limited

Inventor： Carlos Garcia-Tobin ,  Bruce James Mathewson ,  Matthew Lucien Evans ,  Richard Roy Grisenthwaite

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: An apparatus and method are provided for storing a plurality of translation entries in a cache, each translation entry corresponding to one of a plurality of page table entries and defining a translation between a first address and a second address, and encoding control information indicative of an attribute of each page table entry; returning, in response to a lookup querying a first lookup address, a corresponding second address when the first lookup address corresponds to one of the plurality of translation entries stored in the cache; modifying at least some of the control information in response to notification of a modification of the attribute in a page table entry; and retaining in the cache at least one translation entry corresponding to the page table entry for use in a subsequent address lookup querying a corresponding first lookup address in response to the notification of the modification of the attribute in the page table entry.

公开(公告)号：US11636048B2

公开(公告)日：2023-04-25

申请号：US17259785

申请日：2019-06-07

Applicant: Arm Limited

Inventor： Richard Roy Grisenthwaite ,  Graeme Peter Barnes

IPC: G06F12/14 ,  G06F11/07 ,  G06F11/14 ,  G06F12/1027

Abstract: An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address.

公开(公告)号：US11573907B2

公开(公告)日：2023-02-07

申请号：US17269388

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Ruben Borisovich Ayrapetyan ,  Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks. This provides a very flexible and efficient mechanism for performing tag-guarded memory access operations.