公开(公告)号：US11429532B2

公开(公告)日：2022-08-30

申请号：US15501278

申请日：2015-06-23

Applicant: ARM Limited

Inventor： Ali Ghassan Saidi ,  Richard Roy Grisenthwaite

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/0891 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/126 ,  G06F9/30 ,  G06F9/46

Abstract: An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

公开(公告)号：US09946492B2

公开(公告)日：2018-04-17

申请号：US14927725

申请日：2015-10-30

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Stephan Diestelhorst ,  Aasheesh Kolli ,  Ali Ghassan Saidi ,  Peter Chen ,  Thomas Friedrich Wenisch

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C16/10 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/00 ,  G11C16/102

Abstract: A data processing system 2 including non-volatile memory 22 manages the ordering of writes to the non-volatile memory and persist barrier instructions using a persist buffer storing persist buffer data. A write controller responds to the persist buffer data to prevent writing to the non-volatile memory for instructions following a given persist barrier instruction within a sequence of program instructions before the writes to the non-volatile memory which precede that given persist barrier instruction have at least been acknowledged as received by the memory system containing the non-volatile memory. In the case of a multi-core system, cache snooping mechanisms are used to pass persistency dependence data between cores such that strong persist atomicity may be tracked and managed between the cores.

公开(公告)号：US09697136B2

公开(公告)日：2017-07-04

申请号：US14494000

申请日：2014-09-23

Applicant: ARM Limited

Inventor： Ali Ghassan Saidi ,  Anirruddha Nagendran Udipi ,  Matthew Lucien Evans ,  Geoffrey Blake ,  Robert Gwilym Dimond

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/654 ,  G06F2212/681

Abstract: A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.

公开(公告)号：US20190171573A1

公开(公告)日：2019-06-06

申请号：US15831609

申请日：2017-12-05

Applicant: Arm Limited

Inventor： Andrew Christopher Rose ,  Richard Roy Grisenthwaite ,  Ali Ghassan Saidi

IPC: G06F12/0891 ,  G06F12/126 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.

公开(公告)号：US10162762B2

公开(公告)日：2018-12-25

申请号：US14692959

申请日：2015-04-22

Applicant: ARM LIMITED

Inventor： Geoffrey Blake ,  Ali Ghassan Saidi ,  Mitchell Hayenga

IPC: G06F12/1027

Abstract: A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6. The hint generator 20 tracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.

公开(公告)号：US09372811B2

公开(公告)日：2016-06-21

申请号：US13713999

申请日：2012-12-13

Applicant: ARM LIMITED

Inventor： Prakash Shyamlal Ramrakhyani ,  Ali Ghassan Saidi

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F12/08

Abstract: A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value PV stored with each cache line 66 within the cache memory 58. The initial retention priority value set upon inserting a cache line 66 into the cache memory 58 is dependent upon either or both of which of a plurality of sources issued the access memory request that resulted in the insertion or the privilege level of the memory access request resulting in the insertion. The initial retention priority level of cache lines resulting from instruction fetches may be set differently from cache lines resulting from data accesses.

Abstract translation: 数据处理系统包括高速缓存存储器58和高速缓冲存储器控制电路56，用于根据与高速缓存存储器58中的每条高速缓存行66存储的保留优先级值PV应用高速缓存替换策略。在插入高速缓存行时设置的初始保留优先级值 66进入高速缓冲存储器58取决于多个源中的哪一个发出访问存储器请求，导致插入或存储器访问请求的特权级别导致插入。 由指令提取产生的高速缓存行的初始保留优先级可以与由数据访问产生的高速缓存行设置不同。