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公开(公告)号：US11829041B2
公开(公告)日：2023-11-28
申请号：US17312427
申请日：2020-09-07
Inventor： Maoxiu Zhou , Yanping Liao , Yingmeng Miao , Yuntian Zhang , Lei Guo , Ke Dai , Haipeng Yang , Zhihua Sun , Xibin Shao , Zhangtao Wang
IPC: G02F1/1362 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/1368 , G02F1/136227
Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.
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公开(公告)号：US12283218B2
公开(公告)日：2025-04-22
申请号：US18027534
申请日：2022-03-30
Inventor： Wenpeng Ma , Shulin Yao , Yanping Liao , Panhui Zhao , Dongchuan Chen , Pengfei Hu , Zheng Zhang , Yingmeng Miao
Abstract: A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.
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公开(公告)号：US20240428717A1
公开(公告)日：2024-12-26
申请号：US18826136
申请日：2024-09-05
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
Abstract: There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.
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公开(公告)号：US12073807B2
公开(公告)日：2024-08-27
申请号：US18016845
申请日：2022-02-18
Inventor： Wenjie Hou , Cong Wang , Yingmeng Miao , Dongchuan Chen , Jiantao Liu
CPC classification number: G09G3/3677 , G09G3/3688 , H05K1/189 , G09G2320/041 , H05K2201/10136
Abstract: Provided are a display apparatus and a method for driving display apparatus. The display apparatus includes a display substrate; the display substrate includes: gate drive circuit, connected with gate lines disposed in the display area; a plurality of clock signal lines; and a bonding pad; a first circuit board; and a second circuit board; the first circuit board and the second circuit board are independent of each other; the first circuit board is disposed at a side, facing away from the display area, of the second circuit board; the first circuit board and the second circuit board are electrically connected with the bonding pad; the first circuit board is electrically connected with the gate drive circuit via the plurality of clock signal lines; and in an extension direction of the gate line, a width of the first circuit board is smaller than a width of the second circuit board.
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公开(公告)号：US11823640B2
公开(公告)日：2023-11-21
申请号：US17429937
申请日：2020-10-30
Inventor： Chongyang Zhao , Yingmeng Miao , Qiujie Su , Zhihua Sun , Wenjie Hou , Feng Qu
CPC classification number: G09G3/3677 , H01L27/124 , H01L27/1225
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a gate driving circuitry arranged at a peripheral region of the display substrate; n clock signal leads coupled to the gate driving circuitry, each clock signal lead extending in a first direction; and n clock signal lines arranged sequentially in the first direction, each clock signal line extending in a second direction intersecting the first direction, where n is a positive integer greater than 1. The clock signal leads have a same length in the first direction, each clock signal lead extends from a first clock signal line to an nth clock signal line, and each clock signal lead is coupled to a corresponding clock signal line at a position where the clock signal lead intersects the clock signal line.
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Patent Agency Ranking
公开(公告)号：US11796870B2
公开(公告)日：2023-10-24
申请号：US17288963
申请日：2020-09-27
Inventor： Jianhua Huang , Yingmeng Miao , Chongyang Zhao , Zhihua Sun , Yingying Qu , Ting Dong , Yifu Chen , Lingdan Bo , Senwang Li
IPC: G02F1/1343 , G02F1/1362 , G02F1/1335
CPC classification number: G02F1/134372 , G02F1/134309 , G02F1/136286 , G02F1/133512
Abstract: An array substrate, a light control panel, and a display device are disclosed. The array substrate includes a data line layer, a base substrate, a first electrode layer, and a second electrode layer. The first electrode layer includes gate lines, each gate line integrally extends along a first direction, and includes first broken line structures directly connected in sequence in the first direction; the data line layer includes data lines, each data line integrally extends along a second direction; the gate lines and the data lines cross each other to define light control pixel units; the second electrode layer includes common electrodes, each common electrode is provided in at least one light control pixel unit; and at least one gate line at least partially overlaps with an orthographic projection of at least one common electrode on the first electrode layer.
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公开(公告)号：US11749161B2
公开(公告)日：2023-09-05
申请号：US18082691
申请日：2022-12-16
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/08 , G09G2310/0243 , G09G2310/0267 , G09G2310/0286 , G09G2310/08
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US11688745B2
公开(公告)日：2023-06-27
申请号：US17486583
申请日：2021-09-27
Inventor： Cong Wang , Seungmin Lee , Xipeng Wang , Wei Zhang , Benzhi Xu , Xin Zhou , Tao Yang , Yingmeng Miao
IPC: H01L27/12 , G02F1/1368 , G02F1/1345 , G02F1/1362
CPC classification number: H01L27/1244 , G02F1/1368 , G02F1/13452 , G02F1/136227 , G02F1/136286 , G02F2201/122
Abstract: A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different.
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公开(公告)号：US20220399377A1
公开(公告)日：2022-12-15
申请号：US17594832
申请日：2020-12-21
Inventor： Chongyang Zhao , Yingmeng Miao , Zhihua Sun , Feng Qu , Xiaochun Xu
IPC: H01L27/12 , G02F1/1362
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.
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公开(公告)号：US12254849B2
公开(公告)日：2025-03-18
申请号：US18024480
申请日：2022-03-08
Inventor： Yingmeng Miao , Yanping Liao , Dongchuan Chen , Shulin Yao , Jiantao Liu
IPC: G09G3/36
Abstract: A driving method for a display panel and a display apparatus. The driving method includes: acquiring display data of a to-be-displayed image in a current display frame (S100); and loading a data voltage on a data line in the display panel according to the display data, such that each sub-pixel in the display panel is charged with the corresponding data voltage (S200).
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