-
21.发明授权公开(公告)号：US10559282B2
公开(公告)日：2020-02-11
申请号：US15793957
申请日：2017-10-25
发明人： Guangliang Shang , Jung Chul Gyu , Seung Woo Han , Haoliang Zheng , Mingfu Han , Zhihe Jin , Im- Yun- Sik , Jing Lv , Xue Dong
摘要： The present disclosure relates to a pixel driving circuit for switching display resolution, a driving method thereof, and a display apparatus. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch provided thereon, and is connected to at least one of the k second data lines through at least one second switch respectively, and the first switch and the second switch are connected to a signal control unit which is configured to control the first switch to be turned on and the second switch to be turned off when display is to be performed at a first resolution, and control the first switch to be turned off and the second switch to be turned on when display is to be performed at a second resolution.
-
公开(公告)号：US10540938B2
公开(公告)日：2020-01-21
申请号：US15768948
申请日：2017-10-17
发明人： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC分类号： G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
摘要： A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
-
公开(公告)号：US10330975B2
公开(公告)日：2019-06-25
申请号：US15794298
申请日：2017-10-26
发明人： Zhihe Jin , Seungwoo Han , Mingfu Han , Xing Yao , Guangliang Shang , Zhichong Wang , Lijun Yuan , Haoliang Zheng , Yunsik Im
IPC分类号： G02F1/133 , G02F1/13357 , G02F1/1335 , G02F1/1343 , G02F1/19
摘要： The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.
-
24.发明申请公开(公告)号：US20180240393A1
公开(公告)日：2018-08-23
申请号：US15712429
申请日：2017-09-22
发明人： Hui ZHANG , Seung-Woo Han , Yun-Sik Im , Shunhang Zhang , Mingfu Han
IPC分类号： G09G3/20 , H01L27/12 , H01L29/786
CPC分类号： G09G3/2092 , G09G2300/0408 , G09G2300/0426 , G09G2310/0221 , G09G2320/0233 , G09G2320/0686 , G09G2330/021 , G09G2330/028 , H01L27/124 , H01L29/42384 , H01L29/78636 , H01L29/78648
摘要： An array substrate includes a display region including at least two partitions. The array substrate includes a gate driving circuit, first gate electrodes and second gate electrodes. The gate driving circuit is configured to, while inputting a first voltage to the respective first gate electrodes for turning on corresponding thin film transistors according to normal timing, selectively input, to all the second gate electrodes in at least one of the partitions, a second voltage for turning off or turning on all thin film transistors in the partition.
-
公开(公告)号：US20180197455A1
公开(公告)日：2018-07-12
申请号：US15682740
申请日：2017-08-22
发明人： Mingfu Han , Guangliang Shang , Han-Seung- Woo , Xing Yao , Zhihe Jin , Haoliang Zheng , Lijun Yuan , Zhichong Wang
IPC分类号： G09G3/20
摘要： The embodiments of the present disclosure provide a partition-based gate driving method and apparatus and a gate driving unit, and relates to the field of display technology. In the embodiments of the present disclosure, the partition-based gate driving method comprises: generating a control signal according to an acquired human eye observation partition; generating a second clock signal or a third clock signal according to the control signal; and controlling a second output signal according to the second clock signal or controlling a third output signal according to the third clock signal, thereby controlling the display area to be displayed by partitions.
-
公开(公告)号：US11176886B2
公开(公告)日：2021-11-16
申请号：US16319185
申请日：2018-05-14
发明人： Lijun Yuan , Mingfu Han , Zhichong Wang , Haoliang Zheng , Seungwoo Han , Guangliang Shang
IPC分类号： G09G3/3258 , G09G3/3266 , G09G3/3275 , G09G3/3233 , G09G3/3208 , G09G3/3225
摘要： The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality.
-
公开(公告)号：US20210335210A1
公开(公告)日：2021-10-28
申请号：US16485994
申请日：2018-09-06
发明人： Mingfu Han , Guangliang Shang , Xing Yao , Haoliang Zheng
IPC分类号： G09G3/32
摘要： The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.
-
公开(公告)号：US20210201840A1
公开(公告)日：2021-07-01
申请号：US16084027
申请日：2018-04-08
发明人： Guangliang Shang , Liugang Zhou , Haoliang Zheng , Yaoqiu Jing , Mingfu Han , Seungwoo Han
IPC分类号： G09G3/36
摘要： The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.
-
公开(公告)号：US20200258463A1
公开(公告)日：2020-08-13
申请号：US15768309
申请日：2017-10-31
发明人： Jiha Kim , Seungwoo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Zhichong Wang , Mingfu Han , Lijun Yuan , Yunsik IM , Jing Lv , Xue Dong
摘要： A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
-
公开(公告)号：US10504469B2
公开(公告)日：2019-12-10
申请号：US15768948
申请日：2017-10-17
发明人： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC分类号： G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
摘要： A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
-
-
-
-
-
-
-
-
-
搜索结果
49 条记录 (耗时 0.018 秒)
