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56 条记录 (耗时 0.021 秒)

    Shallow trench isolation formation with improved trench edge oxide
    21.
    发明授权
    Shallow trench isolation formation with improved trench edge oxide 失效
    浅沟槽隔离形成，具有改善的沟槽边缘氧化物

    公开(公告)号：US5970363A

    公开(公告)日：1999-10-19

    申请号：US993827

    申请日：1997-12-18

    申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： H01L21/762 ,  H01L21/8242

    CPC分类号： H01L21/76232

    摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.

    摘要翻译： 形成浅沟槽隔离结构，其能够在沟槽边缘处生长高质量的栅极氧化物。 实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。 在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上。 然后抛光停止层被掩蔽到沟槽边缘，并且沟槽中的抛光停止被蚀刻掉。 然后用绝缘材料填充沟槽，将绝缘材料平坦化，并通过蚀刻去除抛光止动件。 因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。 此外，沟槽中不留下抛光停止层，引起不必要的电气效应。

    Dissolvable dielectric method
    23.
    发明授权
    Dissolvable dielectric method 失效
    溶解介电法

    公开(公告)号：US5953626A

    公开(公告)日：1999-09-14

    申请号：US659166

    申请日：1996-06-05

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/7682

    摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

    摘要翻译： 一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。 随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。 在本发明的一个实施例中，在阻挡层上形成第一互连电平。 然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。 在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。 除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。 临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。 在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。 如果需要，气隙电介质可以与多于两个级别的互连一起使用。

    Integrated circuit having horizontally and vertically offset interconnect lines
    25.
    发明授权
    Integrated circuit having horizontally and vertically offset interconnect lines 失效
    集成电路具有水平和垂直偏移的互连线

    公开(公告)号：US5854131A

    公开(公告)日：1998-12-29

    申请号：US655245

    申请日：1996-06-05

    申请人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford Jr. ,  Fred N. Hause ,  William S. Brennan

    发明人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford Jr. ,  Fred N. Hause ,  William S. Brennan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L21/44

    CPC分类号： H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002

    摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.

    摘要翻译： 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。 因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。 交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。 此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。 根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。 封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

    Semiconductor interlevel dielectric having a polymide for producing air gaps
    28.
    发明授权
    Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
    具有用于产生气隙的聚酰亚胺的半导体层间电介质

    公开(公告)号：US5783481A

    公开(公告)日：1998-07-21

    申请号：US659167

    申请日：1996-06-05

    申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002

    摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.

    摘要翻译： 提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。 电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。 当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。 空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。 介电沉积工艺优选包括两个沉积循环。 使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。 聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

    Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery
    30.
    发明授权
    Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery 有权
    用于产生有限隔离沟槽宽度结构的方法和具有围绕其周边的窄隔离沟槽的器件

    公开(公告)号：US6162699A

    公开(公告)日：2000-12-19

    申请号：US181561

    申请日：1998-10-29

    申请人： Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76224 ,  Y10S438/942 ,  Y10S438/945

    摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.

    摘要翻译： 用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构 区域层，多晶硅层和局部互连（LI）层。 一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。 一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。 然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。 然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。 所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。