公开(公告)号：US06204695B1

公开(公告)日：2001-03-20

申请号：US09336357

申请日：1999-06-18

申请人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

发明人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

IPC分类号： H03H19096

CPC分类号： G06F1/10

摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

摘要翻译： 为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。 在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。 逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

公开(公告)号：US06775342B1

公开(公告)日：2004-08-10

申请号：US09684540

申请日：2000-10-06

申请人： Steven P. Young ,  John D. Logue ,  Andrew K. Percey ,  F. Erich Goetting ,  Alvin Y. Ching

发明人： Steven P. Young ,  John D. Logue ,  Andrew K. Percey ,  F. Erich Goetting ,  Alvin Y. Ching

IPC分类号： H04L2500

CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/07

摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.

摘要翻译： 在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。 在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。 作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。 相位控制信号与参考时钟信号的周期的预定分数成比例。 数字移相器可以控制在多种模式下工作。 在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。 在第二固定模式中，数字移相器将延迟引入参考时钟信号。 在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。 在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。

公开(公告)号：US07248491B1

公开(公告)日：2007-07-24

申请号：US11044746

申请日：2005-01-26

申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/1075

摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。

公开(公告)号：US08117577B1

公开(公告)日：2012-02-14

申请号：US12361516

申请日：2009-01-28

申请人： Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

发明人： Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5054 ,  G06F17/5031 ,  G06F2217/84

摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

摘要翻译： 识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。 该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。 该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径 多个子路径，并输出定时路径。

公开(公告)号：US07564283B1

公开(公告)日：2009-07-21

申请号：US10837059

申请日：2004-04-30

申请人： John D. Logue ,  Alvin Y. Ching ,  Wei Guang Lu

发明人： John D. Logue ,  Alvin Y. Ching ,  Wei Guang Lu

IPC分类号： H03L7/06 ,  H03H11/16

CPC分类号： G06F1/10 ,  H03L7/07 ,  H03L7/0814

摘要： An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase shifter is used to directly measure the signal delay through a clock phase shifter of the delay lock loop, thereby directly determining the high frequency and low frequency overhead constants.

摘要翻译： 提供了一种自动校准方案，每次使用延迟锁定环时，校准每个ETT / P周期的等效抽头。 更具体地说，数字移相器用于测量ETT / P周期的等效抽头。 或者，数字移相器用于通过延迟锁定环路的时钟移相器直接测量信号延迟，从而直接确定高频和低频开销常数。

公开(公告)号：US07242633B1

公开(公告)日：2007-07-10

申请号：US11044740

申请日：2005-01-26

申请人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

发明人： Alvin Y. Ching ,  Raymond C. Pang ,  Steven P. Young ,  Thanh Pham

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00

摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。