公开(公告)号：US07345507B1

公开(公告)日：2008-03-18

申请号：US11333991

申请日：2006-01-17

申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

IPC分类号： H01L25/00

CPC分类号： H03K19/177

摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

摘要翻译： 多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 选择码存储电路存储产品选择码。 产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。 产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。 选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。 产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

公开(公告)号：US07230445B1

公开(公告)日：2007-06-12

申请号：US11590336

申请日：2006-10-31

申请人： F. Erich Goetting ,  John K. Jennings ,  Anthony J. Collins ,  Patrick J. Quinn

发明人： F. Erich Goetting ,  John K. Jennings ,  Anthony J. Collins ,  Patrick J. Quinn

IPC分类号： H03K19/003

CPC分类号： H03K19/17732 ,  G01R31/3167 ,  G01R31/318516

摘要： Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

摘要翻译： 描述嵌入可编程逻辑器件中的系统监视器的方法和装置。 系统监视器包括用于在其操作期间配置或重新配置系统监视器的动态重新配置端口接口。 系统监视器包括可经由动态重新配置端口响应于输入而重新配置的模数转换器。

公开(公告)号：US06204691B1

公开(公告)日：2001-03-20

申请号：US09569745

申请日：2000-05-11

申请人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

发明人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

IPC分类号： H03K19094

CPC分类号： H03K19/17744 ,  H03K19/00361 ,  H03K19/1778 ,  H03K19/17788

摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

公开(公告)号：US5365125A

公开(公告)日：1994-11-15

申请号：US919658

申请日：1992-07-23

申请人： F. Erich Goetting ,  Stephen M. Trimberger

发明人： F. Erich Goetting ,  Stephen M. Trimberger

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1736 ,  H03K19/17704

摘要： The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

摘要翻译： 本发明的逻辑单元可用于现场可编程逻辑器件，特别是其中互连结构通过反熔丝互连的器件，并且使用传输晶体管对逻辑单元进行编程。 可以选择性地反转逻辑单元的所有输入引线。 来自一个逻辑单元的输出信号可以级联为相邻单元的输入，以有效地计算广泛的功能。 可选的反馈路径允许单元可选地用于顺序功能，而没有由通过现场编程的连接的反馈路径引起的延迟。 配置单元可以用于选择性地将编程电压施加到互连结构，移位用于配置互连结构的配置信息以及捕获和移出互连线的状态的多个目的。 一个新颖的输出缓冲器允许来自多个源的3状态控制。 一个新的复位电路只允许用作顺序元件的单元被复位，并且只有当复位不会引起与输入数据信号的争用时。

公开(公告)号：US06775342B1

公开(公告)日：2004-08-10

申请号：US09684540

申请日：2000-10-06

申请人： Steven P. Young ,  John D. Logue ,  Andrew K. Percey ,  F. Erich Goetting ,  Alvin Y. Ching

发明人： Steven P. Young ,  John D. Logue ,  Andrew K. Percey ,  F. Erich Goetting ,  Alvin Y. Ching

IPC分类号： H04L2500

CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/07

摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.

摘要翻译： 在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。 在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。 作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。 相位控制信号与参考时钟信号的周期的预定分数成比例。 数字移相器可以控制在多种模式下工作。 在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。 在第二固定模式中，数字移相器将延迟引入参考时钟信号。 在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。 在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。

公开(公告)号：US06448809B2

公开(公告)日：2002-09-10

申请号：US09924356

申请日：2001-08-07

申请人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

发明人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

IPC分类号： G06F738

CPC分类号： H03K19/17744 ,  H03K19/00361 ,  H03K19/1778 ,  H03K19/17788

摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

公开(公告)号：US06429682B1

公开(公告)日：2002-08-06

申请号：US09865813

申请日：2001-05-25

申请人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

发明人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

IPC分类号： H03K19173

CPC分类号： H03M13/09

摘要： A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

摘要翻译： 一种用于可编程逻辑器件（PLD）的总线接口电路，包括连接在两个或多个外部通信电路和配置存储器阵列之间的接口多路复用器。 接口多路复用器协调所选择的一个外部通信电路和分组处理器之间的通信。 分组处理器解译从所选择的外部通信电路在比特流中发送的命令/数据信息。 在默认状态下，接口多路复用器将PLD的双用途输入/输出引脚连接到数据包处理器。 在替代状态下，接口多路复用器将JTAG接口电路连接到分组处理器，以便于通过PLD的JTAG引脚进行配置操作。

公开(公告)号：US06289068B1

公开(公告)日：2001-09-11

申请号：US09102740

申请日：1998-06-22

申请人： Joseph H. Hassoun ,  F. Erich Goetting ,  John D. Logue

发明人： Joseph H. Hassoun ,  F. Erich Goetting ,  John D. Logue

IPC分类号： H03D324

CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/07

摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.

摘要翻译： 延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。 延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。 时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。 耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。 延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。 相位检测器比较参考时钟信号和偏斜时钟信号，以确定延迟线的适当传播延迟。

公开(公告)号：US06262596B1

公开(公告)日：2001-07-17

申请号：US09374471

申请日：1999-08-13

申请人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

发明人： David P. Schultz ,  Lawrence C. Hung ,  F. Erich Goetting

IPC分类号： H03K19177

CPC分类号： H03M13/09

摘要： A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

摘要翻译： 一种用于可编程逻辑器件（PLD）的总线接口电路，包括连接在两个或多个外部通信电路和配置存储器阵列之间的接口多路复用器。 接口多路复用器协调所选择的一个外部通信电路和分组处理器之间的通信。 分组处理器解译从所选择的外部通信电路在比特流中发送的命令/数据信息。 在默认状态下，接口多路复用器将PLD的双用途输入/输出引脚连接到数据包处理器。 在替代状态下，接口多路复用器将JTAG接口电路连接到分组处理器，以便于通过PLD的JTAG引脚进行配置操作。

公开(公告)号：US6086629A

公开(公告)日：2000-07-11

申请号：US985301

申请日：1997-12-04

申请人： Edward S. McGettigan ,  Jennifer T. Tran ,  F. Erich Goetting

发明人： Edward S. McGettigan ,  Jennifer T. Tran ,  F. Erich Goetting

IPC分类号： G06F17/50 ,  G06F3/00

CPC分类号： G06F17/5054 ,  G06F2217/78

摘要： A method of computer aided design of coarse grain FPGA's by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a "local output" (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers. They're referred to as virtual buffers because they serve only a design function and do not actually exist in a CLB. The virtual buffers provide placement directives such as to connect a primitive cell output to another CLB input within some prescribed geographical limit such as within 4 or 6 CLBs of the one in which the buffer is "located".

摘要翻译： 通过采用所选择的原始单元的库，定义在FPGA设计中有用的连接类，以及为相应原始单元的输入和输出分配适当的连接类，从而对粗粒FPGA进行计算机辅助设计的方法。 其中使用的原始单元和定义的互连已经准确地建立了时序和功率参数，从而能够对整个FPGA设计的静态时序和功耗进行更准确的评估。 此外，本发明的方法产生了布置指令，其然后用作执行后续的位置和路由算法的连接标准。 一个这样的布置指令被实现为一些原始单元的“本地输出”（LO），这意味着该特定输出必须连接到本地可配置逻辑块（CLB）内的另一个原始单元输入。 通过使用多个虚拟缓冲器来获得另一个这样的布置指令。 它们被称为虚拟缓冲区，因为它们仅用于设计功能，实际上并不存在于CLB中。 虚拟缓冲器提供放置指令，例如将原始单元输出连接到一些规定的地理限制内的另一个CLB输入，例如在缓冲器所在的4或6个CLB内。