公开(公告)号：US07212396B2

公开(公告)日：2007-05-01

申请号：US10072339

申请日：2002-02-07

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01G9/042

CPC classification number: H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/20

Abstract: A method of fabricating high resistivity thin film resistors. An isolation region is formed on a substrate to isolate the active regions. A polysilicon layer is formed above the substrate. A diffusion barrier layer is formed above the polysilicon layer. Lightly doped ions are implanted in the polysilicon layer. The substrate is annealed at a high temperature. The diffusion barrier layer and the polysilicon layer are patterned to form a high-resistive thin film resistor. Spacers are formed on the sidewalls of the high-resistive thin film resistor.

Abstract translation: 一种制造高电阻薄膜电阻的方法。 在衬底上形成隔离区以隔离有源区。 在衬底上形成多晶硅层。 在多晶硅层上方形成扩散阻挡层。 在多晶硅层中注入轻掺杂离子。 衬底在高温下退火。 扩散阻挡层和多晶硅层被图案化以形成高电阻薄膜电阻器。 隔板形成在高电阻薄膜电阻器的侧壁上。

公开(公告)号：US20060157819A1

公开(公告)日：2006-07-20

申请号：US10905770

申请日：2005-01-20

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L29/00

CPC classification number: H01L29/7833 ,  H01L21/28052 ,  H01L23/5256 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A surface of a semiconductor substrate comprises at least one electrical conduction structure and at least one eFuse. The electrical conduction structure comprises a first poly silicon layer and a first poly silicide layer formed in the first poly silicon layer. The eFuse comprises a second poly silicon layer and a second poly silicide layer formed on the second poly silicon layer. The area of the second poly silicide layer is smaller than the area of the first poly silicide layer.

Abstract translation: 半导体衬底的表面包括至少一个导电结构和至少一个eFuse。 导电结构包括形成在第一多晶硅层中的第一多晶硅层和第一多晶硅化物层。 eFuse包括形成在第二多晶硅层上的第二多晶硅层和第二多晶硅化物层。 第二多晶硅化物层的面积小于第一多晶硅化物层的面积。

公开(公告)号：US07056796B2

公开(公告)日：2006-06-06

申请号：US10725523

申请日：2003-12-03

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78

Abstract: A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Abstract translation: 提供了一种用于制造硅化物的处理方法。 首先，提供具有半导体表面和绝缘表面的半导体结构。 接下来，形成半导体表面上的外延层。 并且，半导体结构被处理。 处理步骤是绝缘表面的去除速度比外延层的去除速度快。 然后，形成外延层上的金属层。 最后，加热外延层形成硅化物。 处理步骤防止绝缘表面形成硅化物，从而降低器件特性的劣化。

公开(公告)号：US20060097406A1

公开(公告)日：2006-05-11

申请号：US10904431

申请日：2004-11-10

Applicant: Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

Inventor： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。 半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US20060030083A1

公开(公告)日：2006-02-09

申请号：US11250826

申请日：2005-10-13

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L21/82

CPC classification number: H01L24/02 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

Abstract translation: 提供一种半导体器件，其包括具有集成电路结构的衬底和其上的图案化金属层。 图案化金属层包括第一图案和第二图案。 第一图案具有不同于第二图案的厚度。 由于基板上的第一图案和第二图案都具有针对其使用而优化的厚度，所以提高了半导体器件的性能。

公开(公告)号：US20050250256A1

公开(公告)日：2005-11-10

申请号：US10839522

申请日：2004-05-04

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L21/82 ,  H01L23/485 ,  H01L23/495 ,  H01L23/525

CPC classification number: H01L24/02 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

Abstract translation: 提供一种半导体器件，其包括具有集成电路结构的衬底和其上的图案化金属层。 图案化金属层包括第一图案和第二图案。 第一图案具有不同于第二图案的厚度。 由于基板上的第一图案和第二图案都具有针对其使用而优化的厚度，所以提高了半导体器件的性能。

公开(公告)号：US6010958A

公开(公告)日：2000-01-04

申请号：US907005

申请日：1997-08-06

Applicant: Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

Inventor： Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/3105 ,  H01L21/76819 ,  Y10S438/937

Abstract: A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

Abstract translation: 一种在制造金属互连件时改善电介质层的平面化的方法，其中使用快速热处理操作以便在介电层局部平坦化之后固化电介质层的暴露表面。 该方法避免了在预金属蚀刻操作期间对介电层的损坏，因此，防止在随后的钨沉积期间残留的钨变成楔形，从而产生可能导致与金属布线接触的短路的桁条。