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    Programmable logic device macrocell with improved capability
    25.
    发明授权
    Programmable logic device macrocell with improved capability 失效
    可编程逻辑器件宏单元，具有改进的能力

    公开(公告)号：US5861760A

    公开(公告)日：1999-01-19

    申请号：US766512

    申请日：1996-12-13

    申请人： Bruce B. Pedersen ,  John C. Costello

    发明人： Bruce B. Pedersen ,  John C. Costello

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17748

    摘要： A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowed. This includes logically combining and registering the unborrowed product terms. The macrocell may include circuitry for feeding back to the AND array of the programmable logic device a combinatorial or registered signal of the macrocell, and also outputting such a combinatorial or registered signal from the macrocell. When a combinatorial signal is fed back, the register of the macrocell can be used for another signal of the macrocell.

    摘要翻译： 用于可编程逻辑器件的宏单元包括用于允许相邻宏单元借用宏单元的各种数量的乘积项的电路。 宏单元可以继续充分利用其不被借用的产品术语。 这包括逻辑上组合和注册未管理的产品术语。 宏小区可以包括用于将可编程逻辑设备的AND阵列反馈给宏小区的组合或注册信号的电路，并且还从宏小区输出这样的组合或注册信号。 当反馈组合信号时，宏单元的寄存器可用于宏单元的另一个信号。

    Apparatus and method for margin testing single polysilicon EEPROM cells
    30.
    发明授权
    Apparatus and method for margin testing single polysilicon EEPROM cells 失效
    单个多晶硅EEPROM单元的边缘测试的装置和方法

    公开(公告)号：US06646919B1

    公开(公告)日：2003-11-11

    申请号：US09874716

    申请日：2001-06-04

    申请人： Raminda U. Madurawe ,  Myron W. Wong ,  John C. Costello ,  James D. Sansbury ,  Bruce F. Mielke

    发明人： Raminda U. Madurawe ,  Myron W. Wong ,  John C. Costello ,  James D. Sansbury ,  Bruce F. Mielke

    IPC分类号： G11C1606

    CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/3427 ,  G11C29/50 ,  G11C29/50004 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558

    摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.

    摘要翻译： 公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。 简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。 本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。 在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。 或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。 电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除 电池的裕度电压进入可测量范围。