摘要:
An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.
摘要:
A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signal.
摘要:
A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signal.
摘要:
A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator.
摘要:
A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.
摘要:
A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.
摘要:
A cable having an electrostatic discharge (ESD) dissipative coating. The cable includes a lead and an ESD dissipative coating operatively coupled to the lead. Other layers such as adhesives and insulating layers can be provided. The ESD dissipative coating can also function as the insulator for the lead.
摘要:
An open write head detection circuit is provided comprising a write head driver circuit, a programmable reference voltage source, a comparator and a pulse width filter. The write head driver circuit generates an voltage sense signal. The comparator compares the voltage sense signal with a reference voltage from the programmable reference voltage source and generates a comparator output signal indicative of whether the voltage sense signal is greater than or less than the reference voltage. The comparator output signal is input to the pulse width filter which generates a latched open head signal in response the voltage sense signal being less than the reference level for a predetermined time measured as a programmable number of write clock cycles.
摘要:
An integrated circuit module is designed with bypass switches in critical places to route signals around specific circuit blocks, e.g. an automatic gain control (AGC) system and an anti-aliasing filter. If there had been significant problems with either block, it can be bypassed and tests of the remaining circuits are possible. This allows all circuits in the module to be tested in the initial pass, reducing the risk of needing a third pass after the known problems were fixed in the second pass. Additionally, the bypass circuits are useful at module production test and for diagnostics in the final product.
摘要:
A write head circuit is provided having improved transient and steady state response. The circuit includes a dynamically coupled damping circuit that is coupled to the write head during transient periods of a write signal to substantially reduce or eliminate overshoot generated by a write head cable. During steady state or data writing periods, the damping circuit is decoupled from the write head to prevent unnecessary loading of the write head. In preferred embodiments, the damping circuit includes a resistor in series with a capacitor, and the damping circuit is coupled in parallel to the write head. The resistor substantially reduces the overshoot of a write signal supplied to the write head, while the capacitor decouples the resistor from the write head during steady state or data write periods.