公开(公告)号：US09569365B2

公开(公告)日：2017-02-14

申请号：US14113723

申请日：2012-05-21

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

IPC分类号： G06F12/0875 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0817

摘要： A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

摘要翻译： 数据处理系统包括多个交易主机，每个具有相关联的本地高速缓冲存储器并且耦合到相干互连电路。 相干互连电路内的监控电路维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。

公开(公告)号：US20110087819A1

公开(公告)日：2011-04-14

申请号：US12923727

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/14

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 所述互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，所述互连电路包括：用于从所述至少一个启动器设备接收事务请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的至少一个路径; 用于将所述接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为响应于屏障事务请求，以通过不允许重新排序来保持在通过所述至少一个路径之一的事务请求流内关于所述屏障事务请求的至少一些事务请求的排序 在所述事务请求流中的所述屏障事务请求之前发生的至少一些事务请求相对于在所述事务请求流中的所述沐浴事务请求之后发生的至少一些事务请求; 其中所述沐浴事务请求包括指示所述事务请求流内的所述事务请求中的哪一个包括所述至少一些其顺序要保持的事务请求的指示符。

公开(公告)号：US08732400B2

公开(公告)日：2014-05-20

申请号：US12923725

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。 所述互连电路包括：用于接收来自所述发起者设备的交易请求的至少一个输入; 至少一个用于向所述接收方设备输出交易请求的输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的多条路径; 其中所述交易请求中的至少一个包括数据存储维护请求，请求在所述数据处理设备内的数据存储器上执行数据存储维护操作; 以及用于将所接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为通过沿着所述多个路径中的至少一个路径发送所述数据存储维护操作来响应于所述数据存储维护操作的接收，所述控制电路被配置为维持在 在沿所述多个路径中的至少一个路径传递的事务请求流内的至少一些关于屏障事务请求的事务请求，使得在事务请求流中的数据存储维护请求之后的至少一些事务请求是 通过屏障事务请求在数据存储维护请求之后。

公开(公告)号：US20110125944A1

公开(公告)日：2011-05-26

申请号：US12923906

申请日：2010-10-13

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request.

摘要翻译： 公开了一种用于经由互连向接收方设备发出交易请求的发起者设备。 所述发起者设备包括：用于从所述互连接收请求并向所述互连发出请求的至少一个端口; 用于产生屏障事务请求的屏障发生器，所述屏障事务请求向所述互连指示通过所述互连的事务请求流内的至少一些事务请求的排序应该通过不允许重新排序所述事务中的至少一些来维持 关于屏障交易请求的交易请求流中的屏障事务请求之前发生的请求; 其中响应于接收到查询至少一个事务请求的子集的进程的同步请求，所述发起者设备响应于所述事务请求的所述至少一个子集内的任何待处理的事务请求的动作，并在所述屏障上生成屏障事务请求 并且经由至少一个端口向互连发出屏障事务请求，并且响应于接收到对屏障事务请求的响应来发出确认信号作为对同步请求的响应。

公开(公告)号：US20110119448A1

公开(公告)日：2011-05-19

申请号：US12923725

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 互连电路被配置为提供数据路由，至少一个启动器设备可经由该路径访问至少一个接收设备。 所述互连电路包括：用于接收来自所述发起者设备的交易请求的至少一个输入; 至少一个用于向所述接收方设备输出交易请求的输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的多条路径; 其中所述交易请求中的至少一个包括数据存储维护请求，请求在所述数据处理设备内的数据存储器上执行数据存储维护操作; 以及用于将所接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为通过沿着所述多个路径中的至少一个路径发送所述数据存储维护操作来响应于所述数据存储维护操作的接收，所述控制电路被配置为维持在 在沿所述多个路径中的至少一个路径传递的事务请求流内的至少一些关于屏障事务请求的事务请求，使得在事务请求流中的数据存储维护请求之后的至少一些事务请求是 通过屏障事务请求在数据存储维护请求之后。

公开(公告)号：US08607006B2

公开(公告)日：2013-12-10

申请号：US12923727

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

摘要翻译： 互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。 所述电路包括：用于从至少一个发起者设备接收交易请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 以及用于在至少一个输入和至少一个输出之间传送事务请求的至少一个路径。 还包括用于将接收到的交易请求从至少一个输入路由到至少一个输出的控制电路，并且响应于屏障事务请求以维持关于业务流内的所述屏障事务请求的至少一些交易请求的排序 沿着所述至少一条路径中的一条通过的请求。 阻塞事务请求包括要保持其顺序的事务请求的指示符。

公开(公告)号：US08463966B2

公开(公告)日：2013-06-11

申请号：US12923906

申请日：2010-10-13

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/00 ,  G06F13/364

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： The initiator device receives requests from and issues transaction requests to a recipient device via an interconnect. A barrier generator generates barrier transaction requests indicating to the interconnect that an ordering of some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request. In response to a synchronize request querying progress of a subset of transaction requests, the initiator device actions any pending transaction requests within the subset of transaction request and the barrier generator generates and issues a barrier transaction request to the interconnect. In response to receiving a response to the barrier transaction request, the initiator device issues an acknowledge signal as a response to the synchronize request.

摘要翻译： 发起者设备通过互连接收来自接收方设备的请求并向接收方设备发出事务请求。 屏障发生器产生屏障事务请求，指示互连，通过互连的事务请求流内的某些事务请求的排序应该通过不允许在屏幕交易请求之前出现的一些事务请求的重新排序来维护 关于屏障交易请求的交易请求流。 响应于查询事务请求的子集的进程的同步请求，发起者设备动作事务请求子集内的任何待处理的事务请求，并且屏障生成器生成并向互连发出屏障事务请求。 响应于接收到对屏障事务请求的响应，发起者设备发出确认信号作为对同步请求的响应。

公开(公告)号：US08463958B2

公开(公告)日：2013-06-11

申请号：US13137363

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device. Thus, the initiator device may not transmit the transaction request again until it has received the credit grant, whereupon it may transmit it along with a credit grant indicator such that it is sure that it will be accepted.

公开(公告)号：US20130042032A1

公开(公告)日：2013-02-14

申请号：US13137363

申请日：2011-08-08

申请人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

发明人： Phanindra Kumar Mannava ,  Jamshed Jalal ,  Ramamoorthy Guru Prasadh ,  Michael Alan Filippo ,  Bruce James Mathewson ,  Timothy Charles Mace

IPC分类号： G06F13/14

CPC分类号： G06F13/364 ,  G06F13/1605

摘要： Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device. Thus, the initiator device may not transmit the transaction request again until it has received the credit grant, whereupon it may transmit it along with a credit grant indicator such that it is sure that it will be accepted.

摘要翻译： 公开了用于生成交易请求的发起者设备和用于接收它们的接收方设备。 收件人设备接受事务请求，其中有可用的缓冲存储用于事务请求。 如果没有可用的存储空间，则确认信号发生器产生并输出指示请求已被接收但尚未被接收方设备接受的拒绝确认信号。 信用发生器可以在缓冲器中保留至少一个可用的存储位置，并为发送未被接收方设备接受的事务请求之一的发起者设备生成信用授予。 授信许可向发起者设备指示存在至少一个保留的存储位置，使得来自发起者设备的后续交易请求将被接收方设备接受。 因此，发起者设备可能不再发送交易请求，直到它已经接收到信用授权为止，因此它可以与信用授权指示符一起发送，从而确保它被接受。

公开(公告)号：US20140052921A1

公开(公告)日：2014-02-20

申请号：US14113723

申请日：2012-05-21

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0817

摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

摘要翻译： 数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。 相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。