公开(公告)号：US20090319707A1

公开(公告)日：2009-12-24

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/40

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US09569365B2

公开(公告)日：2017-02-14

申请号：US14113723

申请日：2012-05-21

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

IPC分类号： G06F12/0875 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0817

摘要： A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

摘要翻译： 数据处理系统包括多个交易主机，每个具有相关联的本地高速缓冲存储器并且耦合到相干互连电路。 相干互连电路内的监控电路维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。

公开(公告)号：US07757027B2

公开(公告)日：2010-07-13

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/00

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US20140052921A1

公开(公告)日：2014-02-20

申请号：US14113723

申请日：2012-05-21

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  Bruce James Mathewson

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0817

摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

摘要翻译： 数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。 相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。

公开(公告)号：US20100235579A1

公开(公告)日：2010-09-16

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓冲存储器，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关联的处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被设置为实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该高速缓存中选择一个或多个数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US20090222816A1

公开(公告)日：2009-09-03

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/455

CPC分类号： G06F12/145

摘要： A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software.

摘要翻译： 提供了一种数据处理装置和方法，用于通过在处理电路上执行的虚拟机来控制对安全存储器的访问。 处理电路执行管理程序软件以支持处理电路上的多个虚拟机的执行。 提供了一种用于存储由处理电路进行访问的数据的存储器系统，该存储器系统包括用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器，该安全存储器仅可通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 由管理程序软件维护和管理可信赖的虚拟机标识符，如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信虚拟机标识符。 因此，响应于当前虚拟机发出的访问请求，地址转换电路仅能够将修改的访问请求作为指定安全存储器内的物理地址的安全访问请求发出，如果可信虚拟机标识符 被设置。 通过这种方法，管理程序软件能够支持多个虚拟机，其中至少一些虚拟机在由管理程序软件控制的条件下可以访问安全存储器。

公开(公告)号：US20070143515A1

公开(公告)日：2007-06-21

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US08418175B2

公开(公告)日：2013-04-09

申请号：US12379082

申请日：2009-02-12

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F12/145

摘要： Processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system stores data for access by the processing circuitry and includes secure memory and non-secure memory . The secure memory is only accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. The hypervisor software sets a trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. The address translation circuitry can only cause the modified access request to be issued as a secure access request to the secure memory if the trusted identifier is set.

摘要翻译： 处理电路执行管理程序软件以支持在处理电路上执行多个虚拟机。 存储器系统存储用于由处理电路访问的数据，并且包括安全存储器和非安全存储器。 安全存储器只能通过安全访问请求访问。 地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定 物理地址。 如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信赖的虚拟机标识符。 如果设置了可信标识符，则地址转换电路只能使经修改的访问请求作为对安全存储器的安全访问请求发出。

公开(公告)号：US08041897B2

公开(公告)日：2011-10-18

申请号：US12223173

申请日：2006-09-18

申请人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

发明人： Stuart David Biles ,  Richard Roy Grisenthwaite ,  David Hennah Mansell

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/127 ,  G06F12/0862

摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.

摘要翻译： 提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。 数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓存，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关处理单元执行访问时的数据值 指令序列 提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。 然后，对于每个高速缓存，缓存维护逻辑被布置以实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别​​的任何优选的执行，从该缓存中选择一个或多个用于逐出的数据值 在那个缓存中。 已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

公开(公告)号：US08271730B2

公开(公告)日：2012-09-18

申请号：US11907265

申请日：2007-10-10

申请人： Frederic Claude Marie Piry ,  Philippe Jean-Pierre Raphalen ,  Norbert Bernard Eugéne Lataille ,  Stuart David Biles ,  Richard Roy Grisenthwaite

发明人： Frederic Claude Marie Piry ,  Philippe Jean-Pierre Raphalen ,  Norbert Bernard Eugéne Lataille ,  Stuart David Biles ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.

摘要翻译： 用于执行数据处理操作的多个处理单元需要访问共享存储器中的数据。 每个具有存储用于该处理单元访问的数据的子集的相关联的高速缓存。 缓存一致性协议确保每个单元访问的数据是最新的。 当输出用于存储在共享存储器中的数据值时，每个单元发出写访问请求。 当写访问请求需要更新相关联的高速缓存和共享存储器时，在高速缓存一致性逻辑内启动一致性操作。 对于包括与发出写访问请求的处理单元相关联的缓存的所有缓存执行一致性操作，以便确保这些高速缓存中的数据保持一致。