公开(公告)号：US09361415B1

公开(公告)日：2016-06-07

申请号：US14503403

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Taranjit Singh Kukal ,  Vikas Kohli

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Various embodiments implement multi-fabric designs by using respective EDA tools associated with multiple design fabrics to access their respective native design data. Each EDA tool has access to and processes or manipulates its corresponding native design data; and no EDA tools have the visibility of the entire multi-fabric electronic design. Requests for actions are automatically transmitted among these EDA tools to instantiate desired EDA tools and to descend or ascend the multi-fabric design structure so that native design data in a particular design fabric are processed by the corresponding EDA tool(s) within the context of the other design fabrics. These techniques enable designers to implement, check, verify, simulate, analyze, probe, and netlist the entire electronic design across multiple design fabric.

Abstract translation: 各种实施例通过使用与多个设计结构相关联的相应EDA工具来访问其各自的本机设计数据来实现多结构设计。 每个EDA工具都可以访问和处理或操纵其对应的本地设计数据; 并且没有EDA工具可以看到整个多结构的电子设计。 在这些EDA工具之间自动传送动作请求，以实例化所需的EDA工具，并下降或上升多结构设计结构，使特定设计结构中的本机设计数据由相应的EDA工具在上下文中进行处理 其他设计面料。 这些技术使设计人员能够跨多个设计架构实施，检查，验证，模拟，分析，探测和整理电子设计。

公开(公告)号：US09348960B1

公开(公告)日：2016-05-24

申请号：US14503404

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Taranjit Singh Kukal ,  Vikas Kohli

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Described are methods and systems for netlisting or probing multi-fabric designs that identify a request for process at least a portion of a multi-fabric electronic design and determine a first partial listing of one or more first circuit components in response to the request by at least identifying first design data in a first design fabric of the one or more first circuit components using a first session of a first electronic design automation (EDA) tool. The methods and systems further automatically transmit a request for action related to the one or more first circuit components from the first session to a second session of a second EDA tool and determine a second partial listing of one or more second circuit components by at least identifying second design data in a second design fabric of the one or more second circuit components using the second session.

Abstract translation: 描述了用于网络列表或探测多结构设计的方法和系统，其识别处理多结构电子设计的至少一部分的请求，并且响应于在第一电路组件的请求确定一个或多个第一电路组件的第一部分列表 使用第一电子设计自动化（EDA）工具的第一会话来最小化所述一个或多个第一电路组件的第一设计结构中的第一设计数据。 所述方法和系统进一步自动地将与所述一个或多个第一电路组件相关的动作请求从第一会话发送到第二EDA工具的第二会话，并且通过至少识别一个或多个第二电路组件来确定第二部分列表 使用第二会话的一个或多个第二电路组件的第二设计结构中的第二设计数据。

公开(公告)号：US09141746B1

公开(公告)日：2015-09-22

申请号：US14231578

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Jean-Noel Pic ,  Stephane Berger

IPC: G06F17/50 ,  G06F3/0484

CPC classification number: G06F17/5068 ,  G06F17/5072

Abstract: A system and method for enabling the display and movement of a boundary box of an instance master inclusive of specific predetermined geometric figures, including master pins, master halo and master boundary edges, is provided. The system and method provides for improved utilization of computer resources and enables users of the present invention to be able to drag and use instance master in their designs more efficiently and rapidly.

Abstract translation: 提供了一种用于实现包括主引脚，主光晕和主边界边缘的特定预定几何图形的实例主体的边界框的显示和移动的系统和方法。 该系统和方法提供了改进的计算机资源的利用，并且使本发明的用户能够更有效和快速地在其设计中拖放和使用实例主设备。

公开(公告)号：US10685167B1

公开(公告)日：2020-06-16

申请号：US16147832

申请日：2018-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Jean-François Alain Lepère ,  Arnold Ginetti

IPC: G06F30/398 ,  G06F3/0484 ,  G06F119/18 ,  G06F111/04 ,  G06F111/20

Abstract: The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.

公开(公告)号：US10346573B1

公开(公告)日：2019-07-09

申请号：US14871929

申请日：2015-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Karun Sharma ,  Roland Ruehl ,  Arnold Ginetti ,  Srihari Sampath

IPC: G06F17/50

Abstract: An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.

公开(公告)号：US10331841B1

公开(公告)日：2019-06-25

申请号：US14997239

申请日：2016-01-15

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Jean-Noel Pic

IPC: G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.

公开(公告)号：US10282505B1

公开(公告)日：2019-05-07

申请号：US15283052

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques identify at least a layout or a portion thereof and determine one or more legal sets of routing tracks for the layout or the portion. One or more figure groups are identified or generated at a first virtual hierarchy, and the one or more first figure groups inherit respective portions of the one or more legal sets of routing tracks. A plurality of legal devices are identified in a layout or a portion thereof, and a figure group is generated at least by determining a boundary for the figure group and enclosing the plurality of layout devices within the boundary. These techniques may modify a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

公开(公告)号：US10210299B1

公开(公告)日：2019-02-19

申请号：US15283042

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout circuit component designs according to the virtual hierarchy. The layout portion may then be abstracted into an abstracted layout portion at least by displaying the plurality of layout circuit component designs and suppressing one or more remaining layout circuit component designs.

公开(公告)号：US10055529B1

公开(公告)日：2018-08-21

申请号：US15283089

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.

公开(公告)号：US09842183B1

公开(公告)日：2017-12-12

申请号：US14869505

申请日：2015-09-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Ginetti ,  Gerard Tarroux ,  Jean-Noel Pic ,  Olivier Arnaud ,  Devendra Deshpande

IPC: G06F17/50 ,  G06F17/24 ,  G06F3/0481 ,  G06F17/30 ,  G06F3/0484 ,  G06F7/00

CPC classification number: G06F17/5072 ,  G06F3/0481 ,  G06F3/04842 ,  G06F7/00 ,  G06F17/24 ,  G06F17/30312 ,  G06F17/30979 ,  G06F17/5022

Abstract: Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.