公开(公告)号：US07511983B2

公开(公告)日：2009-03-31

申请号：US11677630

申请日：2007-02-22

申请人： Hee Bok Kang

发明人： Hee Bok Kang

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22 ,  G11C7/02 ,  G11C7/18

摘要： The present invention relates to a memory device with a hierarchy bit line. In a FeRAM with folded bit lines and opened bit lines, it has a hierarchy bit line where bit line signals in two or more columns commonly share one global bit line signal. In the hierarchy bit line, cell array blocks with the folded bit lines transferred with cell data of FeRAM cells are arranged between a pair of global bit lines in two or more columns, each of sense amps is arranged on the upper and lower edges of each of the cell array blocks, each of the sense amps is shared in the folded bit lines of the top cell array block and the folded bit lines of the bottom cell array block while being alternatively arranged in the neighboring columns, and the sense amps share the pair of global bit lines. The present invention has an effect of providing a cell array structure effectively adapted to construct an ECC circuit because it has a hierarchy construction where bit line signals in two columns or four columns commonly share one global bit line signals.

摘要翻译： 本发明涉及具有层次位线的存储器件。 在具有折叠位线和打开的位线的FeRAM中，它具有层级位线，其中两个或更多列中的位线信号通常共享一个全局位线信号。 在层次位线中，具有与FeRAM单元的单元数据一起传送的折叠位线的单元阵列块布置在两列或更多列中的一对全局位线之间，每个感测放大器布置在每个的每个的上下边缘上 的单元阵列块中，每个感测放大器在顶部单元阵列块的折叠位线和底部单元阵列块的折叠位线共享，同时交替地布置在相邻列中，并且感测放大器共享 一对全局位线。 本发明具有提供有效地构造ECC电路的单元阵列结构的效果，因为它具有层级结构，其中两列或四列中的位线信号通常共享一个全局位线信号。

公开(公告)号：US20090027975A1

公开(公告)日：2009-01-29

申请号：US12127988

申请日：2008-05-28

申请人： Hee Bok Kang ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Suk Kyoung Hong

IPC分类号： G11C5/14

CPC分类号： G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72

摘要： A method is disclosed for driving a phase change memory device including a phase change resistor. The method includes applying a trigger voltage to the phase change resistor for a first write time to preheat the phase change resistor, applying a first write voltage to the phase change resistor for a second write time to control a first state of the phase change resistor, and applying a second voltage to the phase change resistor for a third write time to control a second state of the phase change resistor.

摘要翻译： 公开了一种用于驱动包括相变电阻器的相变存储器件的方法。 该方法包括：将第一写入时间的触发电压施加到相变电阻器，以预热相变电阻器，向第二写入时间施加第一写入电压至相变电阻器，以控制相变电阻器的第一状态， 以及将第二电压施加到所述相变电阻器用于第三写入时间，以控制所述相变电阻器的第二状态。

公开(公告)号：US20090027954A1

公开(公告)日：2009-01-29

申请号：US12146539

申请日：2008-06-26

申请人： Hee Bok Kang ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Suk Kyoung Hong

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026

摘要： A phase change memory device includes a cell array. The cell array includes a phase change resistance cell formed at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a bit line discharge signal in a precharge mode. A column switching unit is configured to selectively control a connection between the bit line and a global bit line in response to a column selecting signal.

摘要翻译： 相变存储器件包括单元阵列。 单元阵列包括形成在字线和位线的交点处的相变电阻单元和被配置为在预充电模式下响应于位线放电信号对位线进行放电的虚设单元。 列切换单元被配置为响应于列选择信号选择性地控制位线和全局位线之间的连接。

公开(公告)号：US20090010037A1

公开(公告)日：2009-01-08

申请号：US11956394

申请日：2007-12-14

申请人： Hee Bok Kang ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Suk Kyoung Hong

IPC分类号： G11C11/22

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/22

摘要： A semiconductor memory device comprises a one-transistor (1-T) field effect transistor (FET) type ferroelectric device connected between a pair of bit lines and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer; a plurality of access transistors connected between the ferroelectric device and the pair of bit lines; and a plurality of port word lines configured to select the plurality of access transistors.

摘要翻译： 一种半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管（1-T）场效应晶体管（FET）型铁电元件，其中不同的沟道电阻根据 铁电层的极性状态; 连接在所述铁电体器件与所述一对位线之间的多个存取晶体管; 以及配置为选择所述多个存取晶体管的多个端口字线。

公开(公告)号：US07417528B2

公开(公告)日：2008-08-26

申请号：US11325486

申请日：2006-01-05

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0701

摘要： A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.

摘要翻译： RFID装置具有非易失性铁电存储器，其包括仅供给高电压的存储单元阵列区域和供给低电压的周边区域，从而降低功耗。 RFID设备包括适于并配置为收发来自外部通信设备的射频信号的天线，适于并配置为响应于从天线接收的射频信号而产生电力电压的模拟块，适配和配置的数字块 从模拟块接收电源电压，将响应信号发送到模拟块并输出存储器控制信号，以及存储器，其被配置为响应于存储器控制信号而产生具有电源电压和访问数据的高电压 。

公开(公告)号：US07408799B2

公开(公告)日：2008-08-05

申请号：US11525812

申请日：2006-09-25

申请人： Hee Bok Kang

发明人： Hee Bok Kang

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22 ,  G06K19/0723

摘要： A nonvolatile ferroelectric memory in an RFID device includes a plurality of word lines, and a plurality of banks each including a cell array. The cell array of one of the banks includes a region to be initialized, wherein the region includes a plurality of memory unit cells each including a ferroelectric capacitor, the memory unit cells being connected to the word lines. The ferroelectric capacitor of a first one of the memory unit cells is connected between a plate line and a cell transistor. The ferroelectric capacitor of a second one of the memory unit cells has one terminal connected to a ground terminal. The first one and the second one of the memory cells are respectively connected to a first one and a second one of the word lines, the first one and the second one of the word lines being connected to each other.

摘要翻译： RFID装置中的非易失性强电介质存储器包括多个字线，以及包括单元阵列的多个存储体。 其中一个单元的单元阵列包括要初始化的区域，其中该区域包括多个存储单元单元，每个单元单元包括铁电电容器，存储单元单元连接到字线。 存储单元单元中的第一个的铁电电容器连接在板线和单元晶体管之间。 存储单元单元的第二个的铁电电容器具有连接到接地端子的一个端子。 第一个和第二个存储单元分别连接到第一个和第二个字线，第一个和第二个字线被彼此连接。

公开(公告)号：US20080158934A1

公开(公告)日：2008-07-03

申请号：US11964472

申请日：2007-12-26

申请人： Hee Bok Kang ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Suk Kyoung Hong

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.

摘要翻译： 具有铁电体器件的半导体存储器件包括沟道区域，漏极区域和形成在衬底中的源极区域，形成在沟道区域上的铁电层以及形成在铁电层上的字线。 根据铁电层的极性状态，不同的沟道电阻被感应到沟道区，通过在强电介质层的读取电压施加读取电压的同时，根据强电介质层的极性状态微分的电池感应电流值进行数据读取动作 字线和感测偏压施加到漏极区域和源极区域中的一个，并且数据写入操作由强电介质层的极性根据施加到字线，漏极区域和漏极区域的电压而改变 源区。

公开(公告)号：US07382641B2

公开(公告)日：2008-06-03

申请号：US10879121

申请日：2004-06-30

申请人： Hee Bok Kang ,  Dong Yun Jeong ,  Jae Hyoung Lim

发明人： Hee Bok Kang ,  Dong Yun Jeong ,  Jae Hyoung Lim

IPC分类号： G11C11/22 ,  G11C5/06

CPC分类号： G11C11/22

摘要： A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a global data bus, and a plurality of data bus switch arrays. Each of the plurality of cell array blocks has a hierarchical bit line architecture including sub bit lines and a main bit line group corresponding to a plurality of unit cells for storing differential data. The plurality of sense amplifier units, corresponding one-by-one to the cell array blocks, sense and amplify the differential data induced on the main bit line group during a sensing operation. The plurality of local data buses, corresponding one-by-one to the sense amplifier units, transfer the differential data outputted from the sense amplifier units and differential data to be transferred to the sense amplifier units. The global data bus, shared by a plurality of the local data buses, transfers the differential data. The plurality of data bus switch arrays selectively couple the local data buses to the global data bus.

摘要翻译： 非挥发性铁电存储器件以高速感测细胞数据。 优选地，非挥发性铁电存储器件包括多个单元阵列块，多个读出放大器单元，多个读出放大器单元，多个本地数据总线，全局数据总线和多个数据总线开关 阵列 多个单元阵列块中的每一个具有分层位线架构，其包括与用于存储差分数据的多个单位单元相对应的子位线和主位线组。 在单元阵列块中逐个对应的多个读出放大器单元在感测操作期间感测并放大在主位线组上感应的差分数据。 将多个本地数据总线对应于读出放大器单元一个一个地传送从读出放大器单元输出的差分数据和要传送到读出放大器单元的差分数据。 由多个本地数据总线共享的全局数据总线传送差分数据。 多个数据总线开关阵列选择性地将本地数据总线耦合到全局数据总线。

公开(公告)号：US07366039B2

公开(公告)日：2008-04-29

申请号：US11320986

申请日：2005-12-30

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： G11C7/00

CPC分类号： G11C11/22 ,  G11C7/16 ,  G11C8/10

摘要： A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

摘要翻译： 具有非易失性铁电存储器的RFID装置调节位线电容以优化位线感测裕度并最小化功耗。 RFID装置具有适于并被配置为向/从外部通信装置发送和接收射频信号的模拟块，适于并被配置为从模拟块接收电力电压和射频信号的数字块，发送响应 信号到模拟块并输出存储器控制信号，以及适配和配置为存储数据并调节位线电容的存储器。

公开(公告)号：US07352634B2

公开(公告)日：2008-04-01

申请号：US11325351

申请日：2006-01-05

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： G11C7/00

CPC分类号： G11C11/22

摘要： A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time. The nonvolatile latch circuit does not require an additional data storage period but detects change of latch data in the active period to store new data in a nonvolatile latch unit. When power is accidentally off, new data are constantly stored in the nonvolatile latch unit, thereby preventing data loss and improving an operating speed without a booting time for restoring data.

摘要翻译： 一种非易失性锁存电路和芯片上的系统，具有相同的特征检测在活动期间锁存数据的变化，以将新数据存储在锁存器中，而不需要额外的数据存储时间。 非易失性锁存电路不需要额外的数据存储周期，而是在活动期间检测锁存数据的变化，以将新数据存储在非易失性锁存单元中。 当电源意外关闭时，新数据不断存储在非易失性锁存单元中，从而防止数据丢失，提高运行速度，而无需启动恢复数据的时间。