公开(公告)号：US07868422B2

公开(公告)日：2011-01-11

申请号：US11280888

申请日：2005-11-16

申请人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

发明人： Kuo-Ting Lee ,  You-Kuo Wu ,  Fu-Hsin Chen ,  An-Ming Chiang

IPC分类号： H01L29/06

CPC分类号： H01L21/761 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833

摘要： The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.

摘要翻译： 本发明公开了一种半导体结构。 第一极性类型的掩埋层构造在半导体衬底上。 在掩埋层上形成第二极性类型的第一外延层。 第二极性类型的第二外延层形成在掩埋层上。 在掩埋层上的第一和第二外延层之间形成第一极性类型的隔离结构。 在第一外延层上形成第二极性类型的第一阱。 在第二外延层上形成第二极性类型的第二阱。 第一极性类型的第三阱形成在隔离结构上的第一和第二阱之间。 隔离结构与埋层和第三阱接口，从而基本上阻挡第一和第二阱之间的漏电流路径。

公开(公告)号：US07655990B2

公开(公告)日：2010-02-02

申请号：US11424530

申请日：2006-06-15

申请人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

发明人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

IPC分类号： H01L29/94

CPC分类号： H01L29/808

摘要： The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.

摘要翻译： 本发明提出了利用由两个耗尽边界形成的夹断机构的电压剪切装置。 可以响应于栅极电压来调节电压限幅装置的限幅电压; 准连接井的缺口; 以及准连接阱的掺杂浓度和深度以及与准连接阱具有互补掺杂极性的阱。 与传统的变压器相比，电压钳位装置可以与微型尺寸的电压降压装置集成在半导体器件内。

公开(公告)号：US20080116539A1

公开(公告)日：2008-05-22

申请号：US11601131

申请日：2006-11-17

申请人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

发明人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/0692

摘要： A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage. In addition, the semiconductor process comprises the steps of forming a deep well with a second type of ions in a substrate with a first type of ions; forming a first doped region with the first type of ions; forming an oxide layer; forming a second doped region in the deep well with the first type of ions; forming a heavily doped region in the deep well with the second type of ions; and forming a first electrode on a Schottky contact on the deep well and a second electrode on an Ohmic contact on the heavily doped region.

摘要翻译： 提供了一种肖特基器件及其制造方法。 肖特基器件包括衬底，深阱，肖特基接触和欧姆接触。 衬底掺杂有第一类型的离子。 深阱掺杂有第二类离子，并形成在衬底中。 肖特基接触器与深井接触第一电极。 欧姆接触接触具有重掺杂区域的第二电极，第二种类型的离子在深阱中。 其中深阱具有在肖特基接触下形成的宽度的几何间隙，第一类型的离子和第二类型的离子是互补的，并且间隙的宽度调节击穿电压。 此外，半导体工艺包括以下步骤：在具有第一类型离子的衬底中形成具有第二类型离子的深阱; 形成具有所述第一类型离子的第一掺杂区域; 形成氧化物层; 在所述深井中用所述第一类型的离子形成第二掺杂区域; 在深井中用第二类离子形成重掺杂区; 以及在深阱上的肖特基接触上形成第一电极，在重掺杂区域上的欧姆接触上形成第二电极。

公开(公告)号：US20070247225A1

公开(公告)日：2007-10-25

申请号：US11407537

申请日：2006-04-19

申请人： Chih-Feng Huang ,  Chiu-Chih Chiang ,  You-Kuo Wu ,  Wei-Hsuan Huang ,  Ta-yung Yang

发明人： Chih-Feng Huang ,  Chiu-Chih Chiang ,  You-Kuo Wu ,  Wei-Hsuan Huang ,  Ta-yung Yang

IPC分类号： H03F1/36

CPC分类号： H02M1/36 ,  H02M2001/0006

摘要： A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.

摘要翻译： 提出了一种电源转换器的开关电路。 它包括电压限幅装置，电阻装置，第一晶体管和第二晶体管。 电压限幅装置耦合到输入电压。 第一晶体管与用于切换输入电压的电压限幅装置串联连接。 第二晶体管被耦合以响应于控制信号来控制第一晶体管和电压限幅装置。 当第二晶体管截止时，电阻器件提供偏置电压以接通压限器件和第一晶体管。 一旦第二晶体管导通，第一晶体管被截止并且电压限幅器件被负偏置。 钳位装置被开发以钳位第一晶体管的最大电压。

公开(公告)号：US20070102759A1

公开(公告)日：2007-05-10

申请号：US11271933

申请日：2005-11-10

申请人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Ming Chiang

发明人： Fu-Hsin Chen ,  Wen-Hua Huang ,  Kuo-Ting Lee ,  You-Kuo Wu ,  An-Ming Chiang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823418 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823481

摘要： A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

公开(公告)号：US20060220179A1

公开(公告)日：2006-10-05

申请号：US11097744

申请日：2005-04-01

申请人： You-Kuo Wu ,  Edward Chiang

发明人： You-Kuo Wu ,  Edward Chiang

IPC分类号： H01L29/00

CPC分类号： H01L29/0882 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming an improved isolation junction in an LDMOS structure to reduce current leakage at high operating Voltages including forming doped regions in a buried layer prior to forming an overlying epitaxial region including doped isolation regions followed by a drive-in process to form a continuous isolation region by intermixing the doped regions formed in the buried layer with the overlying doped isolation regions.

摘要翻译： 一种用于在LDMOS结构中形成改进的隔离结的方法，以减少在高工作电压下的电流泄漏，包括在形成包含掺杂隔离区域的上覆外延区域之前形成掩埋层中的掺杂区域，随后进行形成连续 通过将形成在掩埋层中的掺杂区域与上覆的掺杂隔离区域相混合来实现。

公开(公告)号：US08803544B2

公开(公告)日：2014-08-12

申请号：US13279390

申请日：2011-10-24

申请人： Chih-Cheng Ku ,  Shan-Cheng Sun ,  You-Kuo Wu

发明人： Chih-Cheng Ku ,  Shan-Cheng Sun ,  You-Kuo Wu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2884

摘要： An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present.

摘要翻译： 提供集成电路芯片。 集成电路芯片包括焊盘，第一电阻器，第二电阻器，第一开关，第二开关和控制器。 第一电阻器和第一开关串联连接在焊盘和第一参考电压端子之间。 第二电阻器和第二开关串联连接在焊盘和第二参考电压端子之间。 控制器根据错误确定机制选择性地打开和关闭第一和第二开关。 误差确定机构确定是否存在与焊盘相关联的错误状况。

公开(公告)号：US20120280708A1

公开(公告)日：2012-11-08

申请号：US13279390

申请日：2011-10-24

申请人： CHIH-CHENG KU ,  Shan-Cheng Sun ,  You-Kuo Wu

发明人： CHIH-CHENG KU ,  Shan-Cheng Sun ,  You-Kuo Wu

IPC分类号： G01R31/26

CPC分类号： G01R31/2884

摘要： An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present.

摘要翻译： 提供集成电路芯片。 集成电路芯片包括焊盘，第一电阻器，第二电阻器，第一开关，第二开关和控制器。 第一电阻器和第一开关串联连接在焊盘和第一参考电压端子之间。 第二电阻器和第二开关串联连接在焊盘和第二参考电压端子之间。 控制器根据错误确定机制选择性地打开和关闭第一和第二开关。 误差确定机构确定是否存在与焊盘相关联的错误状况。

公开(公告)号：US08268691B2

公开(公告)日：2012-09-18

申请号：US13180194

申请日：2011-07-11

申请人： William Wei-Yuan Tien ,  Fu-Hsin Chen ,  Jui-Wen Lin ,  You-Kuo Wu

发明人： William Wei-Yuan Tien ,  Fu-Hsin Chen ,  Jui-Wen Lin ,  You-Kuo Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers.The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor.

摘要翻译： 提供半导体器件及其制造方法。 在半导体衬底中形成有源区的实施例，其中有源区由隔离区界定; 在所述有源区内形成第一掺杂区; 在所述有源区上形成栅电极，其中所述栅电极覆盖所述第一掺杂区的一部分; 在所述栅电极的侧壁上形成至少一个电介质层; 在介电层上形成一对间隔物; 以及形成第二掺杂区域，该第二掺杂区域基本上在与所述间隔物中的一个相邻的所述第一掺杂区域的所述部分内，并且与所述间隔物之一间隔开 第一和第二掺杂区域可以形成如HVMOS晶体管中的双扩散漏极结构。

公开(公告)号：US20080001195A1

公开(公告)日：2008-01-03

申请号：US11426941

申请日：2006-06-28

申请人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

发明人： Chiu-Chih Chiang ,  Chih-Feng Huang ,  You-Kuo Wu ,  Long Shih Lin

IPC分类号： H01L29/94

CPC分类号： H01L27/092 ,  H01L21/823892

摘要： The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.

摘要翻译： 高压集成电路包括P基板。 在衬底中设置N阱势垒。 形成P阱的分离的P扩散区域设置在基板中用作隔离结构。 低压控制电路位于N阱屏障外。 浮动电路位于N阱屏障内。 为了在浮置电路和衬底之间形成高压结屏障，浮动电路的器件的最大空间受到限制。