公开(公告)号：US20100290284A1

公开(公告)日：2010-11-18

申请号：US12708725

申请日：2010-02-19

申请人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

发明人： Chun-Pei Wu ,  Chia-Ta Shieh ,  Chih-Wei Hung ,  Mars Chen

IPC分类号： G11C16/02 ,  G11C11/34

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568

摘要： An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.

摘要翻译： 集成电路结构包括电可擦除可编程只读存储器（EEPROM）阵列，其包括排列成行和列的EEPROM单元; 沿列方向延伸的多条字线和多条漏极线以及沿行方向延伸的多条源极线。 多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 多个漏极线中的每一个连接到同一列中的EEPROM单元的漏极，其中多个漏极线都不被EEPROM单元的相邻列共享。 多个源极线中的每一个连接到同一行中的EEPROM单元的源极。

公开(公告)号：US20100006974A1

公开(公告)日：2010-01-14

申请号：US12172687

申请日：2008-07-14

申请人： Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

发明人： Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

IPC分类号： H01L23/58 ,  H01L21/762

CPC分类号： H01L27/11568 ,  H01L29/4234 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

摘要翻译： 本公开提供了一种制造微电子器件的方法。 该方法包括在半导体衬底中形成凹陷的浅沟槽隔离（STI）特征，在相邻的两个凹入的STI特征之间限定半导体区域; 在所述半导体区域内形成隧道电介质特征; 在凹陷的STI特征和隧道电介质特征上形成氮化物层; 蚀刻氮化物层以在凹陷STI特征内形成氮化物开口; 通过氮化物开口部分地去除凹陷的STI特征，导致氮化物层和凹陷STI特征之间的间隙; 以及在所述氮化物层的表面上形成第一电介质材料，以密封所述氮化物开口。

公开(公告)号：US20060286746A1

公开(公告)日：2006-12-21

申请号：US11154381

申请日：2005-06-15

申请人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

发明人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

摘要： A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.

摘要翻译： 闪速存储器包括衬底，控制栅极，沟槽，源极区域，隔离结构，漏极区域，公共源极线，浮置栅极，隧道电介质层和介电层。 控制栅极和沟槽分别位于衬底上的第一和第二方向上。 源极区域在衬底中并且在控制栅极的一侧上形成沟槽。 隔离结构填充源区域之间的沟槽。 漏极区域位于隔离结构之间的控制栅极另一侧的衬底中。 公共源极线在衬底内部的第二方向上并且电连接到源极区域。 此外，浮置栅极位于源极和漏极区域之间的控制栅极和衬底之间。 隧道电介质层设置在浮置栅极和衬底之间，并且介电层设置在浮动栅极和控制栅极之间。

公开(公告)号：US06979620B1

公开(公告)日：2005-12-27

申请号：US11126301

申请日：2005-05-11

申请人： Chun-Pei Wu ,  Huei-Huarng Chen ,  Hong-Chi Chen ,  Hsuan-Ling Kao

发明人： Chun-Pei Wu ,  Huei-Huarng Chen ,  Hong-Chi Chen ,  Hsuan-Ling Kao

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105

CPC分类号： H01L21/28273 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531

摘要： A method for fabricating a flash memory cell is provided. After an ONO dielectric layer is formed on a first conductive layer over a tunnel oxide layer, a second conductive layer is formed on the ONO dielectric layer. Then, patterning the second conductive layer to form a periphery region comprising an exposed portion of a semiconductor substrate and a memory cell region comprising the left second conductive layer. During the present process, the ONO dielectric layer is protected from being exposed in various solvents and gases with the second conductive layer. Thus, a flash memory cell with a high-quality ONO gate dielectric layer, without increasing complexity of the process and additional masks, is obtained.

摘要翻译： 提供一种制造闪存单元的方法。 在隧道氧化物层上的第一导电层上形成ONO电介质层之后，在ONO电介质层上形成第二导电层。 然后，图案化第二导电层以形成包括半导体衬底的暴露部分和包括左第二导电层的存储单元区域的外围区域。 在本工艺过程中，ONO介电层被保护不被暴露在各种溶剂和气体中与第二导电层。 因此，获得具有高质量ONO栅介质层的闪存单元，而不增加工艺的复杂性和附加掩模。