公开(公告)号：US20060286746A1

公开(公告)日：2006-12-21

申请号：US11154381

申请日：2005-06-15

申请人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

发明人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

摘要： A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.

摘要翻译： 闪速存储器包括衬底，控制栅极，沟槽，源极区域，隔离结构，漏极区域，公共源极线，浮置栅极，隧道电介质层和介电层。 控制栅极和沟槽分别位于衬底上的第一和第二方向上。 源极区域在衬底中并且在控制栅极的一侧上形成沟槽。 隔离结构填充源区域之间的沟槽。 漏极区域位于隔离结构之间的控制栅极另一侧的衬底中。 公共源极线在衬底内部的第二方向上并且电连接到源极区域。 此外，浮置栅极位于源极和漏极区域之间的控制栅极和衬底之间。 隧道电介质层设置在浮置栅极和衬底之间，并且介电层设置在浮动栅极和控制栅极之间。

公开(公告)号：US07619277B2

公开(公告)日：2009-11-17

申请号：US11154381

申请日：2005-06-15

申请人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

发明人： Chun-Pei Wu ,  Huei-Huang Chen ,  Wen-Bin Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

摘要： A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.

摘要翻译： 闪速存储器包括衬底，控制栅极，沟槽，源极区域，隔离结构，漏极区域，公共源极线，浮置栅极，隧道电介质层和介电层。 控制栅极和沟槽分别位于衬底上的第一和第二方向上。 源极区域在衬底中并且在控制栅极的一侧上形成沟槽。 隔离结构填充源区域之间的沟槽。 漏极区域位于隔离结构之间的控制栅极另一侧的衬底中。 公共源极线在衬底内部的第二方向上并且电连接到源极区域。 此外，浮置栅极位于源极和漏极区域之间的控制栅极和衬底之间。 隧道电介质层设置在浮置栅极和衬底之间，并且介电层设置在浮动栅极和控制栅极之间。

公开(公告)号：US06787056B2

公开(公告)日：2004-09-07

申请号：US10067260

申请日：2002-02-07

申请人： Wen-Bin Tsai ,  Ching-Yu Chang ,  Chun-Pei Wu ,  Huei-Huang Chen ,  Samuel C. Pan

发明人： Wen-Bin Tsai ,  Ching-Yu Chang ,  Chun-Pei Wu ,  Huei-Huang Chen ,  Samuel C. Pan

IPC分类号： B44C122

CPC分类号： H01L21/31055 ,  H01L21/31111

摘要： A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.

摘要翻译： 可以应用使用各向异性蚀刻的平面化方法来平坦化具有基板上的不平坦表面的绝缘层。 将H 2 SO 4，H 3 PO 4，HF和H 2 O混合以形成蚀刻溶液。 将衬底放置在蚀刻溶液中以使蚀刻溶液以流速通过绝缘层的表面以蚀刻绝缘层。 经过一段时间的蚀刻时间后，可获得具有更平坦表面的绝缘层。

公开(公告)号：US08044675B2

公开(公告)日：2011-10-25

申请号：US12766935

申请日：2010-04-26

申请人： Yung-Yu Wu ,  Huei-Huang Chen ,  Wei-Fen Chiang

发明人： Yung-Yu Wu ,  Huei-Huang Chen ,  Wei-Fen Chiang

IPC分类号： G01R31/00

CPC分类号： G01R1/0408 ,  H05K1/0296 ,  H05K2201/09027 ,  H05K2201/09227 ,  H05K2201/10325

摘要： A testing apparatus includes a public test board, a single DUT (device under test) test board and a holder. The public test board includes a plurality of public test channel sets each having a plurality of public signal terminals for receiving test signals. On the single DUT test board, a plurality first signal terminals are arranged according to the pin layout of a DUT, a plurality second signal terminals are arranged according to the terminal layout of a public channel set, and a plurality traces are arranged for electrically connecting corresponding first and second signal terminals. The holder can connect the pins of the DUT to corresponding first signal terminals.

摘要翻译： 测试设备包括公共测试板，单个DUT（被测器件）测试板和持有器。 公共测试板包括多个公共测试通道组，每个公共测试通道组具有用于接收测试信号的多个公共信号端子。 在单个DUT测试板上，根据DUT的引脚布局布置多个第一信号端子，根据公共通道组的端子布局布置多个第二信号端子，并且布置多个迹线用于电连接 对应的第一和第二信号端子。 保持器可以将DUT的引脚连接到相应的第一个信号端子。

公开(公告)号：US07706999B2

公开(公告)日：2010-04-27

申请号：US11806499

申请日：2007-05-31

申请人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Jie-Wei Huang ,  Huei-Huang Chen

发明人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Jie-Wei Huang ,  Huei-Huang Chen

IPC分类号： G01R31/26 ,  G06F17/40 ,  G06F19/00

CPC分类号： G01R31/3167

摘要： The invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a precision measurement unit, a signal transformation module, and a microprocessor. The precision measurement unit is coupled to the device under test for providing a testing signal and receiving a measurement signal generated according to the testing signal. The signal transformation module is coupled to the precision measurement unit for receiving the measurement signal and transforming the measurement signal to a signal measurement result according to a predetermined manner. The microprocessor is coupled to the precision measurement unit and the signal transformation module for examining the signal measurement result to determine a test result for the device under test.

摘要翻译： 本发明公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括精密测量单元，信号变换模块和微处理器。 精密测量单元耦合到被测设备，以提供测试信号并接收根据测试信号产生的测量信号。 信号变换模块耦合到精度测量单元，用于接收测量信号，并根据预定方式将测量信号变换成信号测量结果。 微处理器耦合到精密测量单元和信号变换模块，用于检查信号测量结果，以确定被测器件的测试结果。

公开(公告)号：US20080243409A1

公开(公告)日：2008-10-02

申请号：US11806499

申请日：2007-05-31

申请人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Jie-Wei Huang ,  Huei-Huang Chen

发明人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Jie-Wei Huang ,  Huei-Huang Chen

IPC分类号： G01R13/00 ,  G01R13/02

CPC分类号： G01R31/3167

摘要： The invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a precision measurement unit, a signal transformation module, and a microprocessor. The precision measurement unit is coupled to the device under test for providing a testing signal and receiving a measurement signal generated according to the testing signal. The signal transformation module is coupled to the precision measurement unit for receiving the measurement signal and transforming the measurement signal to a signal measurement result according to a predetermined manner. The microprocessor is coupled to the precision measurement unit and the signal transformation module for examining the signal measurement result to determine a test result for the device under test.

摘要翻译： 本发明公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括精密测量单元，信号变换模块和微处理器。 精密测量单元耦合到被测设备，以提供测试信号并接收根据测试信号产生的测量信号。 信号变换模块耦合到精度测量单元，用于接收测量信号，并根据预定方式将测量信号变换成信号测量结果。 微处理器耦合到精密测量单元和信号变换模块，用于检查信号测量结果，以确定被测器件的测试结果。

公开(公告)号：US08847654B2

公开(公告)日：2014-09-30

申请号：US13167730

申请日：2011-06-24

申请人： Yang-Han Lee ,  Yung-Yu Wu ,  Huei-Huang Chen

发明人： Yang-Han Lee ,  Yung-Yu Wu ,  Huei-Huang Chen

IPC分类号： H03L5/00 ,  G01R15/22

CPC分类号： G01R15/22

摘要： In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.

摘要翻译： 在控制电路中，光耦合器用于隔离噪声，通用放大器用于调节增益，因此逻辑测试器可以与模拟信号中具有不同规格和工作电压电平差的继电器配合测试模拟信号 测量模块 控制模块的每个控制电路的移位寄存器还将测试数据信号发送到下一级控制电路，使得逻辑测试器可以通过仅使用一个I同时将多个位输出到多个控制电路和多个模拟测量模块 / O端口。

公开(公告)号：US20100153800A1

公开(公告)日：2010-06-17

申请号：US12638368

申请日：2009-12-15

申请人： Yung-Yu Wu ,  Huei-Huang Chen

发明人： Yung-Yu Wu ,  Huei-Huang Chen

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31926 ,  G01R31/31725

摘要： The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.

摘要翻译： 本发明提供了一种逻辑测试仪。 在一个实施例中，逻辑测试器耦合到多个测试设备，并且包括功能发生器和模式比较器。 函数发生器产生初始代码序列作为被测试器件的输入信号，将测试器件的输出信号固定为第一值，然后产生功能代码序列作为测试器件的输入信号，以触发输出信号 被测试的设备从第一个值变为第二个值。 模式比较器在产生功能代码序列之后将被测试设备的输出信号转换为多个比特流，计算与比特流中的第一个值对应的比特数，根据比特数来估计被测试设备的延迟时间 ，并输出被测试设备的延迟时间。

公开(公告)号：US20120163798A1

公开(公告)日：2012-06-28

申请号：US13167730

申请日：2011-06-24

申请人： Yang-Han Lee ,  Yung-Yu Wu ,  Huei-Huang Chen

发明人： Yang-Han Lee ,  Yung-Yu Wu ,  Huei-Huang Chen

IPC分类号： H04B17/00

CPC分类号： G01R15/22

摘要： In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.

摘要翻译： 在控制电路中，光耦合器用于隔离噪声，通用放大器用于调节增益，因此逻辑测试器可以与模拟信号中具有不同规格和工作电压电平差的继电器配合测试模拟信号 测量模块 控制模块的每个控制电路的移位寄存器还将测试数据信号发送到下一级控制电路，使得逻辑测试器可以通过仅使用一个I同时将多个位输出到多个控制电路和多个模拟测量模块 / O端口。

公开(公告)号：US08099659B2

公开(公告)日：2012-01-17

申请号：US12638368

申请日：2009-12-15

申请人： Yung-Yu Wu ,  Huei-Huang Chen

发明人： Yung-Yu Wu ,  Huei-Huang Chen

IPC分类号： G06F11/00

CPC分类号： G01R31/31926 ,  G01R31/31725

摘要： The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.

摘要翻译： 本发明提供了一种逻辑测试仪。 在一个实施例中，逻辑测试器耦合到多个测试设备，并且包括功能发生器和模式比较器。 函数发生器产生初始代码序列作为被测试器件的输入信号，将测试器件的输出信号固定为第一值，然后产生功能代码序列作为测试器件的输入信号，以触发输出信号 被测试的设备从第一个值变为第二个值。 模式比较器在产生功能代码序列之后将被测试设备的输出信号转换为多个比特流，计算与比特流中的第一个值对应的比特数，根据比特数来估计被测试设备的延迟时间 ，并输出被测试设备的延迟时间。