公开(公告)号：US20060044015A1

公开(公告)日：2006-03-02

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US07545299B2

公开(公告)日：2009-06-09

申请号：US11902663

申请日：2007-09-24

申请人： Jui-Yuan Tsai ,  Chi-Kung Kuan

发明人： Jui-Yuan Tsai ,  Chi-Kung Kuan

IPC分类号： H03M1/62

CPC分类号： H03M1/1028 ,  G09G5/006 ,  H03M1/123 ,  H04N9/642

摘要： The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.

摘要翻译： 本发明公开了一种模拟前端装置，包括校准单元和至少一个转换电路。 转换电路包括钳位器，复用器，电压缓冲器和模数转换器。 夹持器接收图像信号并重置图像信号的直流电压电平以产生钳位信号。 复用器接收钳位信号和测试信号，并根据选择信号输出钳位信号或测试信号。 电压缓冲器放大钳位信号或测试信号以产生缓冲信号。 模数转换器将缓冲器信号转换为数字信号。 校准单元根据测试信号产生增益校正值，并根据增益校正值校准数字信号的增益偏移。

公开(公告)号：US07279931B2

公开(公告)日：2007-10-09

申请号：US11162001

申请日：2005-08-25

申请人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

发明人： Chao-Cheng Lee ,  Yung-Hao Lin ,  Wen-Chi Wang ,  Jui-Yuan Tsai

IPC分类号： H03K19/0175

CPC分类号： H01L27/0928 ,  H03K17/102

摘要： An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

摘要翻译： 输出级结构包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管，其中MOS晶体管是用双阱工艺制造的。 第一PMOS晶体管具有耦合到电源电压（VDD）的源极和耦合到第一电压的栅极。 第二PMOS晶体管具有耦合到第一PMOS晶体管的漏极的源极，耦合到第二电压的栅极和耦合到输出焊盘的漏极。 第一NMOS晶体管具有耦合到输出焊盘的漏极和耦合到第三电压的栅极。 第二NMOS晶体管具有耦合到第一NMOS晶体管的源极的漏极，耦合到第四电压的栅极和耦合到地的源极。

公开(公告)号：US07253764B2

公开(公告)日：2007-08-07

申请号：US11463014

申请日：2006-08-08

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/502 ,  H03M1/66 ,  H03M3/464

摘要： A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

摘要翻译： 参考电压产生电路包括：第一电容器; 第二电容器; 参考电压采样电容器; 用于交替地将第二电容器耦合到预定电压以允许第二电容器对预定电压进行采样的第一开关; 用于将第二电容器交替地耦合到第一电容器的第二开关，以允许第二电容器与第一电容器重新分配电荷，以便产生参考电压; 以及第三开关，用于将第一电容器交替地耦合到参考电压采样电容器，以允许参考电压采样电容器与第一电容器重新分配电荷，以便输出参考电压。

公开(公告)号：US20070046523A1

公开(公告)日：2007-03-01

申请号：US11463014

申请日：2006-08-08

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/502 ,  H03M1/66 ,  H03M3/464

摘要： A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

摘要翻译： 参考电压产生电路包括：第一电容器; 第二电容器; 参考电压采样电容器; 用于交替地将第二电容器耦合到预定电压以允许第二电容器对预定电压进行采样的第一开关; 用于将第二电容器交替地耦合到第一电容器的第二开关，以允许第二电容器与第一电容器重新分配电荷，以便产生参考电压; 以及第三开关，用于将第一电容器交替地耦合到参考电压采样电容器，以允许参考电压采样电容器与第一电容器重新分配电荷，以便输出参考电压。

公开(公告)号：US07042373B2

公开(公告)日：2006-05-09

申请号：US10907652

申请日：2005-04-11

申请人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

发明人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chia-Liang Chiang ,  Chao-Cheng Lee

IPC分类号： H03M1/10

CPC分类号： H03M1/1038 ,  H03M1/442

摘要： A pipeline ADC includes a pipeline structure having a plurality of analog-to-digital converting units cascaded in series; and a correcting unit coupled to the pipeline structure for correcting an output value of the pipeline structure according to a set of calibration constants. One of the analog-to-digital converting units contains a capacitor switching circuit. During error measurement of the pipeline ADC, the capacitor switching circuit switches to change capacitance allocation of the analog-to-digital converting unit so as to obtain the set of calibration constants.

摘要翻译： 流水线ADC包括具有串联级联的多个模数转换单元的流水线结构; 以及校正单元，其耦合到所述流水线结构，用于根据一组校准常数校正所述流水线结构的输出值。 模数转换单元之一包含电容器切换电路。 在流水线ADC的误差测量期间，电容器切换电路切换以改变模数转换单元的电容分配，以获得一组校准常数。

公开(公告)号：US07019552B2

公开(公告)日：2006-03-28

申请号：US10724779

申请日：2003-12-02

申请人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03K17/16

CPC分类号： H03F1/56

摘要： The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal. Each of the resistor units and the impedance matching resistor unit includes a plurality of resistors in symmetric configuration.

摘要翻译： 具有有源终端的线路驱动器包括：具有反相输出端子，非反相输出端子，反相输入端子和非反相输入端子的差分放大器; 耦合到所述反相输入端的第一电阻器单元; 耦合到所述非反相输出端子的阻抗匹配电阻器单元; 和电阻反馈网络，具有对称配置的多个电阻器。 电阻反馈网络还包括：耦合到阻抗匹配电阻器单元和反相输入端子的第二电阻器单元; 耦合到非反相输出端子和反相输入端子的第三电阻器单元; 耦合到所述阻抗匹配电阻器单元和所述反相输入端子的第四电阻器单元; 以及耦合到反相输出端子和反相输入端子的第五电阻器单元。 每个电阻器单元和阻抗匹配电阻器单元包括多个对称配置的电阻器。

公开(公告)号：US08446405B2

公开(公告)日：2013-05-21

申请号：US12562113

申请日：2009-09-17

申请人： Szu-Ping Chen ,  Jui-Yuan Tsai ,  Cheng-Jui Chen

发明人： Szu-Ping Chen ,  Jui-Yuan Tsai ,  Cheng-Jui Chen

IPC分类号： G06F3/038

CPC分类号： G09G5/006 ,  H04N5/185

摘要： A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

摘要翻译： DC电平再分配方法包括以下步骤：接收多对差分信号的所有正信号和一个负信号; 将多对差分信号中指定的一对差分信号的正信号的DC电平固定为参考，以便调整所指定的一对差分信号的负信号的DC电平，以产生经调整的负信号 ; 并且将所指定的差分信号对的经调整的负信号作为参考，以便调整除指定的差分信号对之外的其它对差分信号的正信号的DC电平。 DC再分配方法可以用在显示系统中。

公开(公告)号：US08290065B2

公开(公告)日：2012-10-16

申请号：US11878564

申请日：2007-07-25

申请人： Jui-Yuan Tsai ,  Chao-Hsin Lu

发明人： Jui-Yuan Tsai ,  Chao-Hsin Lu

IPC分类号： H04N7/12

CPC分类号： H04N5/0675

摘要： The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.

摘要翻译： 本发明公开了一种包括视频源系统，传输介质和电视系统的图像处理系统。 视频源系统和电视系统的图像处理系统配备有附加的数模转换器和附加的模拟 - 数字转换器。

公开(公告)号：US08130422B2

公开(公告)日：2012-03-06

申请号：US11892393

申请日：2007-08-22

申请人： Jui-Yuan Tsai

发明人： Jui-Yuan Tsai

IPC分类号： H04N1/38

CPC分类号： H04N9/68 ,  G09G5/006 ,  H04N5/16 ,  H04N5/18 ,  H04N9/72

摘要： An image processing device is provided which comprises an input unit and an analog front end circuit with DC inputs. According to the invention, no capacitor is installed in the input unit and no clamper is installed in the AFE circuit with DC inputs. By appropriately selecting a comparing voltage and adding a level shifter or a compensation circuit, the invention can still generate an accurate digital signal.

摘要翻译： 提供一种图像处理装置，其包括具有DC输入的输入单元和模拟前端电路。 根据本发明，输入单元中没有安装电容器，在具有直流输入的AFE电路中没有安装钳位器。 通过适当地选择比较电压并添加电平移位器或补偿电路，本发明仍然可以产生精确的数字信号。