公开(公告)号：US07965213B1

公开(公告)日：2011-06-21

申请号：US12717910

申请日：2010-03-04

申请人： Chang-Shun Liu ,  Tse-Chi Lin ,  Yu-Hsuan Tu ,  Kang-Wei Hsueh

发明人： Chang-Shun Liu ,  Tse-Chi Lin ,  Yu-Hsuan Tu ,  Kang-Wei Hsueh

IPC分类号： H03M1/66

CPC分类号： H03M1/0665 ,  H03M1/74

摘要： An element-selecting method is utilized for selecting the converting elements of the DAC to perform the digital-to-analog conversion. The element-selecting method first determines whether the selected times of the converting elements are all equal or not. When the selected times of the converting elements are all equal, the element-selecting method determines a shifting-step according to the input signal and the number of the converting elements; otherwise, the element-selecting method determines the shifting-step to be a predetermined value. The element-selecting method then selects a converting element from the DAC by means of separating the converting element from a last selected converting element by the shifting-step. In this way, the error accumulated because of the mismatch of the converting elements is eliminated, and the toggle rate of the DAC is reduced. Hence, the glitch and the dynamic errors of the DAC are reduced, improving the performance of the DAC.

摘要翻译： 元件选择方法用于选择DAC的转换元件以进行数模转换。 元素选择方法首先确定转换元素的所选择的时间是否全部相等。 当转换元件的所选择的时间全部相等时，元件选择方法根据输入信号和转换元件的数量确定移位步长; 否则，元件选择方法将移位步骤确定为预定值。 然后，元素选择方法通过借助于通过移位步骤将转换元件与最后选择的转换元件分离，从DAC中选择转换元件。 以这种方式，消除了由于转换元件不匹配而累积的误差，并且DAC的切换速率降低。 因此，减小了DAC的毛刺和动态误差，提高了DAC的性能。

公开(公告)号：US20090115524A1

公开(公告)日：2009-05-07

申请号：US12266073

申请日：2008-11-06

申请人： Chang-Shun LIU

发明人： Chang-Shun LIU

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/3028 ,  H03F2203/30033 ,  H03F2203/45644

摘要： The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

摘要翻译： 本发明涉及一种输出级电路及其运算放大器。 在输出级电路中，响应于从运算放大器中的放大电路输出的小信号，将晶体管的栅极中的一个耦合到偏置晶体管的栅极和电平移位器。 此外，偏置晶体管的栅极电压由电压产生电路控制，以控制输出级电路的晶体管的DC偏置。 因此，不再需要用于补偿输出级电路的晶体管的额外的频率补偿部件，并且通过本发明可以实现节省电路布局面积和成本。

公开(公告)号：US07456769B2

公开(公告)日：2008-11-25

申请号：US11459364

申请日：2006-07-24

申请人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

发明人： Wen-Chi Wang ,  Chang-Shun Liu ,  Chao-Cheng Lee ,  Jui-Yuan Tsai

IPC分类号： H03M3/00

CPC分类号： G11C27/024 ,  G11C27/026

摘要： A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

摘要翻译： 参考电压产生电路包括具有第一端和第二端的第一电容器; 具有第三端和第四端的第二电容器; 用于选择性地将预定电压耦合到第一电容器的第一端的第一开关; 第二开关，用于选择性地将第二电容器的第三端耦合到第一电容器的第一端; 用于选择性地将第一电容器的第一端耦合到参考电压电平的第三开关; 以及用于选择性地将第一电容器的第二端耦合到参考电压电平的第四开关; 其中所述第一电容器在第一级中对所述预定电压进行采样，并且在第二级中将电荷重新分配给所述第二电容器。

公开(公告)号：US20080030620A1

公开(公告)日：2008-02-07

申请号：US11878890

申请日：2007-07-27

申请人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chang-Shun Liu

发明人： Jui-Yuan Tsai ,  Wen-Chi Wang ,  Chang-Shun Liu

IPC分类号： H03M1/12

CPC分类号： H04N5/14

摘要： An analog front end circuit is provided, which comprises at least one converting circuit. Each converting circuit further comprises a clamper, a low-pass filter, an input buffer and a sigma-delta analog-to-digital converter. By using the sigma-delta analog to digital converter, the invention not only increases the resolution, but reduces the order of an anti-aliasing filter, therefore reducing the size and the power consumption of the analog circuit.

摘要翻译： 提供了一种模拟前端电路，其包括至少一个转换电路。 每个转换电路还包括钳位器，低通滤波器，输入缓冲器和Σ-Δ模数转换器。 通过使用Σ-Δ模数转换器，本发明不仅提高了分辨率，而且降低了抗混叠滤波器的次序，从而减小了模拟电路的尺寸和功耗。

公开(公告)号：US07728669B2

公开(公告)日：2010-06-01

申请号：US12266073

申请日：2008-11-06

申请人： Chang-Shun Liu

发明人： Chang-Shun Liu

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/3028 ,  H03F2203/30033 ,  H03F2203/45644

摘要： The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

摘要翻译： 本发明涉及一种输出级电路及其运算放大器。 在输出级电路中，响应于从运算放大器中的放大电路输出的小信号，将晶体管的栅极中的一个耦合到偏置晶体管的栅极和电平移位器。 此外，偏置晶体管的栅极电压由电压产生电路控制，以控制输出级电路的晶体管的DC偏置。 因此，不再需要用于补偿输出级电路的晶体管的额外的频率补偿部件，并且通过本发明可以实现节省电路布局面积和成本。

公开(公告)号：US07675446B2

公开(公告)日：2010-03-09

申请号：US12032527

申请日：2008-02-15

申请人： Chang Shun Liu

发明人： Chang Shun Liu

IPC分类号： H03M1/66

CPC分类号： H03M3/452 ,  H03M3/424

摘要： A filter applied in a sigma-delta modulator includes an integrator, a signal attenuator and a feedback circuit, in which these components are connected in series sequentially to form a local feedback circuit. The integrator integrates an input signal to output an integral signal. Accordingly, the signal attenuator attenuates the integral signal to output an attenuation signal to the local feedback circuit so as to share a part of attenuation amount to reduce the chip area of the sigma-delta modulator.

摘要翻译： 应用在Σ-Δ调制器中的滤波器包括积分器，信号衰减器和反馈电路，其中这些组件被顺次串联连接以形成局部反馈电路。 积分器集成输入信号以输出积分信号。 因此，信号衰减器衰减积分信号以将衰减信号输出到本地反馈电路，以便共享衰减量的一部分以减小Σ-Δ调制器的芯片面积。

公开(公告)号：US20090040087A1

公开(公告)日：2009-02-12

申请号：US12187869

申请日：2008-08-07

申请人： Chang-Shun Liu ,  Yi-Chang Tu ,  Wen-Chi Wang

发明人： Chang-Shun Liu ,  Yi-Chang Tu ,  Wen-Chi Wang

IPC分类号： H03M1/66

CPC分类号： H03M1/0665 ,  H03M1/66 ,  H03M3/502

摘要： A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.

摘要翻译： 公开了一种数据加权平均电路，其包括查找单元和存储单元。 本发明使用查找表来加速电路操作。 此外，操作延迟不受数据加权平均电路的各种顺序和输入数据的各种位宽的影响。

公开(公告)号：US20070247341A1

公开(公告)日：2007-10-25

申请号：US11735517

申请日：2007-04-16

申请人： Chang-Shun Liu

发明人： Chang-Shun Liu

IPC分类号： H03M3/00

CPC分类号： H03M3/32 ,  H03M1/0682 ,  H03M1/365 ,  H03M3/424 ,  H03M3/452

摘要： A sigma-delta modulator includes a first adder, a filter, a quantizer and a digital-to-analog converter. The first adder receives an input signal and an analog signal and subtracts the analog signal from the input signal to output a processed signal. The filter receives the processed signal to output a filtered signal. The quantizer receives the filtered signal to generate an output signal. The quantizer works based on a first positive reference voltage and a first negative reference voltage. The digital-to-analog converter generates the analog signal according to the output signal and outputs the analog signal to the first adder. The digital-to-analog converter works based on a second positive reference voltage and a second negative reference voltage. A difference between the first positive reference voltage and the first negative reference voltage is smaller than a difference between the second positive reference voltage and the second negative reference voltage.

摘要翻译： Σ-Δ调制器包括第一加法器，滤波器，量化器和数 - 模转换器。 第一加法器接收输入信号和模拟信号，并从输入信号中减去模拟信号，以输出处理后的信号。 滤波器接收经处理的信号以输出滤波信号。 量化器接收经滤波的信号以产生输出信号。 量化器基于第一正参考电压和第一负参考电压工作。 数模转换器根据输出信号产生模拟信号，并将模拟信号输出到第一加法器。 数模转换器基于第二正参考电压和第二负参考电压工作。 第一正参考电压和第一负参考电压之间的差小于第二正参考电压和第二负参考电压之间的差。

公开(公告)号：US07948414B2

公开(公告)日：2011-05-24

申请号：US12538153

申请日：2009-08-09

申请人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

发明人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

IPC分类号： H03M3/00

CPC分类号： H03M3/424 ,  H03M3/454

摘要： A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

摘要翻译： 用于接收模拟输入信号以产生数字输出信号的Δ-Σ模数转换装置包括减法单元，量化器和反馈单元。 减法单元用于执行减法函数以根据模拟输入信号和反馈信号产生减去的信号。 量化器耦合到减法单元，用于执行量化，以根据减法信号产生量化信号。 反馈单元耦合在减法单元和量化器之间，用于根据量化信号向减法单元提供反馈信号。 减法单元布置成减小量化器的信号输入摆幅。

公开(公告)号：US20090115527A1

公开(公告)日：2009-05-07

申请号：US12265361

申请日：2008-11-05

申请人： Chang-Shun Liu

发明人： Chang-Shun Liu

IPC分类号： H03F3/16

CPC分类号： H03F3/45183 ,  H03F1/086 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2203/30015 ,  H03F2203/45526 ,  H03F2203/45626 ,  H03F2203/45668

摘要： The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

摘要翻译： 本发明涉及一种输出级电路及其运算放大器。 在输出级电路中，响应于从运算放大器中的放大电路输出的小信号，将晶体管的栅极中的一个耦合到偏置晶体管的栅极和电平移位器。 此外，偏置晶体管的栅极电压由电压产生电路控制，以控制输出级电路的晶体管的DC偏置。 因此，不需要用于补偿输出级电路的晶体管的额外的频率补偿分量，并且通过本发明可以实现节省电路布局面积和成本。