公开(公告)号：US06649473B1

公开(公告)日：2003-11-18

申请号：US10330777

申请日：2002-12-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L21/28273

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract translation: 一种制造闪存的浮动栅极的方法。 在半导体衬底上形成有源区。 在有源区域中依次形成第一绝缘层，第一导电层和掩模层。 去除掩模层的一部分以形成第一开口。 形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。 在第二导电层上形成第二绝缘层以填充第一开口。 进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。 去除第二和第三绝缘层以形成第二开口。 第四绝缘层填充在第二开口中。 除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。

公开(公告)号：US06475894B1

公开(公告)日：2002-11-05

申请号：US10052622

申请日：2002-01-18

Applicant: Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

Inventor： Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

IPC: H01L218247

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.

Abstract translation: 本发明提供一种制造闪速存储器的浮动栅极的方法。 首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。 然后形成栅极氧化物层和第一多晶硅层。 第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。 牺牲绝缘体填充到凹部中。 然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。 在第一多晶硅层的侧壁上形成多晶硅间隔物。 在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。 然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。 最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。 在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。 因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。

公开(公告)号：US08557673B1

公开(公告)日：2013-10-15

申请号：US13476251

申请日：2012-05-21

Applicant: Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

Abstract translation: 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US20130146954A1

公开(公告)日：2013-06-13

申请号：US13429448

申请日：2012-03-26

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

Abstract: The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.

Abstract translation: 本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。 隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。 掩埋位线设置在基板中并沿第二方向延伸。 字线设置在基板中沿第一方向延伸。 漏极区域设置在未被字线覆盖的有源区域中。 电容器设置在基板上并电连接到漏极区域。

公开(公告)号：US07960241B2

公开(公告)日：2011-06-14

申请号：US12698322

申请日：2010-02-02

Applicant: Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/90

Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

Abstract translation: 堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07682902B2

公开(公告)日：2010-03-23

申请号：US11949786

申请日：2007-12-04

Applicant: Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

Inventor： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC: H01L21/336

CPC classification number: H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract translation: 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US08779494B2

公开(公告)日：2014-07-15

申请号：US13426825

申请日：2012-03-22

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

IPC: H01L29/94

CPC classification number: H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

Abstract: The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.

Abstract translation: 本公开涉及高k金属栅极随机存取存储器。 存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。 衬底具有多个沟槽，并且位线单元布置在衬底上。 源极区域设置在位线单元上，栅极结构设置在源极区域上。 每个栅极结构具有形成在其中的金属栅极和沟道区域。 栅极结构顶部带有漏极区域。 字线单元布置在源区和漏区之间。 电容单元设置在漏极区域上。 还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

公开(公告)号：US08703562B2

公开(公告)日：2014-04-22

申请号：US13426832

申请日：2012-03-22

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

IPC: H01L21/8238

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.

Abstract translation: 随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。

公开(公告)号：US20130119448A1

公开(公告)日：2013-05-16

申请号：US13343668

申请日：2012-01-04

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L28/90

Abstract: A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.

Abstract translation: 存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。