Abstract:
Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
Abstract:
A wafer alignment system aligns a wafer by checking the alignment marks formed on the back surface of the wafer. A number of guiding rays are used to determine the corresponding alignment mark on the back of the wafer to ensure that the wafer is properly aligned. The alignment system of the invention also includes a wafer stage and a fixed base, wherein the wafer stage and the fixed base contains a number of apertures that allow the guiding rays to pass through and strike on the alignment marks on the wafer.
Abstract:
An exposure has at least two wafer pads for holding wafers at the same time to perform different tasks including exposing a wafer, aligning a wafer, and loading or unloading a wafer synchronously. The exposure of the invention includes an exposing unit, a wafer supporting unit and a alignment beam scan unit. The wafer-supporting unit contains at least two wafer pads for holding wafers. The alignment beam scan unit contains an interferometer for detecting the interference patterns formed by the alignment beams and the alignment marks on the wafers. The tasks of aligning a wafer, and exposing a wafer, or loading/unloading a wafer can be performed on the wafers placed on each individual wafer pad synchronously.
Abstract:
IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.
Abstract:
A network fabric may divide a physical connection into a plurality of VLANs as defined by IEEE 802.1Q. Moreover, many network fabrics use Priority Flow Control to identify and segregate network traffic based on different traffic classes or priorities. Current routing protocols define only eight traffic classes. In contrast, a network fabric may contain thousands of unique VLANs. When network congestion occurs, network devices (e.g., switches, bridges, routers, servers, etc.) can negotiate to pause the network traffic associated with one of the different traffic classes. Pausing the data packets associated with a single traffic class may also stop the data packets associated with thousands of VLANs. The embodiments disclosed herein permit a network fabric to individually pause VLANs rather than entire traffic classes.
Abstract:
A network node that forwards traffic of a converged network received from a source end node receives a second message addressed to the network node, but intended for the source end node. The second message includes at least a portion of a first message originated by the source end node and previously forwarded by the network node. The network node extracts from the first message a source identifier of the source end node in a first communication protocol and determines by reference to a data structure a destination address of the second message in a second communication protocol. The network node modifies the second message to include the destination address and forwards the second message toward the source end node in accordance with the destination address.
Abstract:
Assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device is provided. In a given processing period, a source is selected in a manner that maintains fairness in the selection process. A corresponding sink is selected for the selected source based on processing efficiency. If, due to assignment constraints, no sink is available for the selected source, the selected source is retained for selection in the next scheduling period, to maintain fairness. In this case, to optimize efficiency, a most efficient currently available sink is identified and a source for providing work to that sink is selected.
Abstract:
A display module and a manufacturing method thereof are provided. The display module comprises a casing, an optical element and a display panel. The casing has an upper portion. The optical element is disposed in the casing. The display panel comprises a color filter substrate and a thin film transistor substrate. The color filter substrate is located within and toward the casing. The thin film transistor substrate is connected to the color filter substrate and connected to the upper portion of the casing.
Abstract:
A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, a source is selected in a manner that maintains fairness in the selection process. A corresponding sink is selected for the selected source based on processing efficiency. If, due to assignment constraints, no sink is available for the selected source, the selected source is retained for selection in the next scheduling period, to maintain fairness. In this case, to optimize efficiency, a most efficient currently available sink is identified and a source for providing work to that sink is selected.
Abstract:
A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.